Self-feedback Memory Read Path Architecture for Latency Reduction
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Solution Overview
Problem
Existing electronic memory devices are limited by latency due to dependence on external clocking rates, which restricts data transmission time and flexibility in column selection, leading to potential conflicts between external clock signals and internal bit line sensing ready signals.
Innovation Solution
A memory read apparatus with a data read path circuit and control apparatus that utilizes self-feedback signals for synchronization, allowing internal timing control independent of external clock rates, and includes bit line switches, data line sense amplifiers, and latches to manage data transfer efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If pipeline stages are shortened to improve data access latency, then data access latency is reduced, but data transmission time is limited by maximum external clock rate
Solution Approach 1:
The patent implements self-feedback control signals that monitor the readiness of bit line sensing and automatically adjust the timing of column selection and data transfer. This feedback mechanism allows the system to operate independently of external clock rate limitations, enabling faster data transmission while maintaining proper synchronization throughout the pipeline stages.
Solution Approach 2:
The system transitions from static clock-synchronized operation to dynamic self-timed operation. The pipeline stages are no longer constrained by fixed clock edges but instead adapt their timing based on actual sensing completion and data readiness, allowing optimal performance across varying conditions and enabling shorter pipeline stages without external clock rate penalties.
2Speed
If external clock rate is increased to improve data transmission speed, then data transmission speed increases, but conflicts arise between external clock signals and internal bit line sensing ready signals
Solution Approach 1:
The system uses self-generated control signals that are internally synchronized to actual sensing events rather than externally imposed clock signals. The bit line sensing ready signals directly trigger subsequent operations, eliminating the need for external clock coordination and preventing timing conflicts entirely. Each stage serves itself by responding to actual readiness conditions.
3Reliability
If pipeline stages are lengthened to accommodate external clock timing, then signal synchronization is maintained, but data access latency increases
Solution Approach 1:
Self-feedback control signals provide continuous monitoring and adjustment of timing throughout the pipeline. This feedback ensures that synchronization is maintained based on actual data readiness rather than fixed stage durations, allowing each stage to operate at optimal speed while maintaining proper coordination between bit line sensing, column selection, and data output.
Data Source
AI summary
A memory reading apparatus transfers digital data from a memory array that is independent of external clocking rate, where the data transmission time is not limited by the external clock period, and the internal timing of controls permits flexible column selection and no conflicts in the timing between external clock signals and internal bit line sensing ready signal. The memory read apparatus has a data read path circuit and a memory read control apparatus. The data read path circuit is in communication with the memory to acquire the selected data read from the memory, synchronize the selected data, and transfer the selected data from the memory. The memory read control apparatus is in communications with the data read path circuit for selecting the data to be read from the memory, for providing self-feedback signals for synchronizing the selected data for transfer from the memory.