SEM Image Generation Using Hotspot Maps for Wafer Fault Prediction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing complexity of circuit patterns in semiconductor manufacturing due to reduced pitch sizes in lithography processes leads to faults in wafers, causing defects in semiconductor devices and reducing reliability and productivity.
Innovation Solution
A method using a machine learning model with a backbone network, hotspot segmentation network, and SEM image generation network to generate a scanning electron microscope (SEM) image, identifying fault areas by analyzing layout images and generating hotspot maps, trained using loss functions based on optical diameters and SEM image discrimination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the pitch of circuit patterns is decreased to increase circuit integration, then circuit design complexity increases, but manufacturing precision deteriorates due to faults in the wafer
Solution Approach 1:
The patent performs preliminary detection of hotspot areas in the layout image before the actual lithography process. By using a backbone network to extract features and a hotspot segmentation network to identify potential fault areas in advance, the system can predict where defects may occur and take preventive measures, thus resolving the contradiction between increased circuit integration and manufacturing precision
Solution Approach 2:
The patent introduces an intermediate hotspot map as a mediator between the layout image and the final SEM image. This hotspot map highlights potential fault areas and is used to guide the SEM image generation network, allowing the system to account for manufacturing variations without actually performing the lithography process, thereby maintaining precision while enabling complex circuit design
2Reliability
If fault detection is performed on actual wafers to ensure reliability, then measurement precision improves, but productivity decreases due to additional processing time
Solution Approach 1:
The patent creates a virtual copy of the wafer by generating a simulated SEM image from the layout image using deep learning networks. This virtual wafer copy contains predicted fault information that can be analyzed without handling actual wafers, thereby maintaining high detection accuracy while eliminating the time-consuming physical processing steps and improving productivity
Solution Approach 2:
The system performs fault detection preliminarily by analyzing the layout image and generating hotspot maps before actual wafer fabrication. This preliminary action identifies potential issues in the design stage, allowing for early corrections without requiring extensive physical testing, thus maintaining reliability while reducing overall processing time
Data Source
AI summary
A method includes extracting first feature data by applying a backbone network of a machine learning model to a layout image representing a design for a target pattern, applying a hotspot segmentation network of the machine learning model to the first feature data, the hotspot segmentation network configured to generate a hotspot map representing a hotspot area of the layout image corresponding to a fault, obtaining, from the hotspot segmentation network, second feature data, and generating a scanning electron microscope (SEM) image of a wafer by applying an SEM image generation network of the machine learning model to the first feature data and the second feature data.