SEM Metrology Guided by Wafer Topography Thresholds
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Solution Overview
Problem
Current pattern wafer geometry (PWG) tools have poor spatial resolution, fail to detect micro-level defects, and lack vertical information, leading to pattern failures and mismatch with critical dimension (CD) scanning electron microscope (SEM) data, especially in wafers with high topography variations.
Innovation Solution
A method and system that combine a wafer topography measurement system with a scanning electron microscope (SEM), using a controller to generate a metrology sampling plan based on topography thresholds, enabling high-resolution defect identification and correlation of surface height variations with defect maps, and measuring critical dimension variations with respect to design overlays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If PWG tools are used to measure wafer topography, then measurement coverage is achieved, but spatial resolution is poor and micro-level defects cannot be detected
Solution Approach 1:
The patent segments the measurement process into two distinct stages: first, a low-resolution PWG tool performs comprehensive wafer-wide topography measurement to identify regions of interest; second, a high-resolution SEM performs detailed inspection only in those specific regions. This segmentation allows the system to achieve both broad measurement coverage and high spatial resolution without requiring a single tool to do both.
Solution Approach 2:
The patent introduces an intermediary component - a controller that processes PWG data, identifies regions with topography variations exceeding a threshold, and generates a sampling plan for the SEM. This intermediary bridges the gap between the low-resolution PWG measurement system and the high-resolution SEM, enabling coordinated operation and optimal defect detection.
2Measurement precision
If PWG tools scan the entire wafer, then comprehensive coverage is obtained, but time consumption increases and productivity decreases
Solution Approach 1:
The patent applies preliminary action by using the PWG tool to pre-scan the entire wafer and identify regions with significant topography variations before the SEM inspection. This preliminary step creates a targeted sampling plan that guides the SEM to focus only on critical areas, thereby reducing the overall measurement time while maintaining high defect detection accuracy.
Solution Approach 2:
Instead of having the high-resolution SEM scan the entire wafer (excessive action), the patent applies partial action by limiting the SEM inspection to only those regions where topography variations exceed a defined threshold. This partial inspection approach maintains high measurement precision while significantly improving productivity by avoiding unnecessary scanning of low-risk areas.
3Productivity
If high topography variation areas are inspected with low resolution, then measurement speed is maintained, but vertical information and defect confirmation are lost
Solution Approach 1:
The patent transitions from a two-dimensional top-down view (PWG measurement) to a three-dimensional detailed inspection (SEM measurement) for regions with high topography variations. This dimensional change enables the system to capture vertical height information and confirm defects in areas where topography variations are significant, without sacrificing overall measurement speed.
Data Source
AI summary
A wafer topography measurement system can be paired with a scanning electron microscope. A topography threshold can be applied to wafer topography data about the wafer, which was obtained with the wafer topography measurement system. A metrology sampling plan can be generated for the wafer. This metrology sampling plan can include locations in the wafer topography data above the topography threshold. The scanning electron microscope can scan the wafer using the metrology sampling plan and identify defects.