Semi-Cascoded Current Mirror for High-Linearity Bandwidth
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Solution Overview
Problem
Current mirror circuits face challenges in achieving high linearity and wide signal bandwidth, as linearity is often traded off against bandwidth and power, limiting their dynamic range in applications such as communication, military, and industrial systems.
Innovation Solution
The implementation of semi-cascoding current mirror arrangements, which include transistors in a common-emitter configuration with additional semi-cascoding stages and a two-terminal passive network, reduces nonlinearity by allowing the base terminal voltage to swing with the output signal, thereby mitigating the miller effect and improving linearity and bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional current mirror circuit is used, then the circuit structure is simple, but the linearity and bandwidth are limited due to third-order nonlinear current from base-collector junction parasitic capacitances
Solution Approach 1:
The current mirror circuit is segmented into multiple stages: a common-emitter stage and a common-base semi-cascoding stage. This segmentation isolates the nonlinear base-collector capacitance effects to specific stages, allowing each stage to be optimized for different functions (signal amplification vs. linearity improvement) without requiring complete circuit redesign.
Solution Approach 2:
The common-base transistor Q3 acts as an intermediary between the common-emitter transistor Q2 and the output transistor Q4. This intermediary stage buffers and transforms the signal, reducing the direct impact of parasitic capacitances on the overall linearity while maintaining signal integrity and enabling better bandwidth performance.
2Manufacturing precision
If the base terminal voltage is allowed to swing with the output signal, then the miller effect is mitigated and linearity improves, but the circuit requires additional components and configuration complexity
Solution Approach 1:
The base terminal voltage of transistor Q2 is made dynamic by coupling it to the output signal through the common-base stage. This dynamic voltage swing compensates for the miller effect caused by base-collector junction capacitances, reducing third-order nonlinear current and improving linearity without requiring fixed biasing arrangements.
3Speed
If high frequency operation is required, then bandwidth must be increased, but nonlinearity from parasitic capacitances becomes more significant
Solution Approach 1:
The circuit transitions from a single-stage common-emitter configuration to a two-dimensional architecture combining common-emitter and common-base stages. This dimensional expansion in circuit topology allows simultaneous optimization for high-frequency bandwidth (through the common-base stage's low input capacitance) and linearity (through reduced miller effect), resolving the trade-off that plagues single-stage designs.
Data Source
AI summary
An example current mirror arrangement includes a current mirror circuit, configured to receive an input current signal at an input transistor Q1 and output a mirrored signal at an output transistor Q2. The arrangement further includes a semi-cascoding circuit that includes transistors Q3, Q4, and a two-terminal passive network. The transistor Q3 is coupled to, and forms a cascode with, the output transistor Q2. The transistor Q4 is coupled to the transistor Q3. The base/gate of the transistor Q3 is coupled to a bias voltage Vref, and the base/gate of the transistor Q4 is coupled to a bias voltage Vref1 via the two-terminal passive network. Nonlinearity of the output current from such a current mirror arrangement may be reduced by selecting appropriate impedance of the two-terminal passive network and selecting appropriate bias voltages Vref and Vref1.