Semi-Cascoded Current Mirror for Linearity and Bandwidth
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Solution Overview
Problem
Current mirrors struggle to maintain high linearity and wide signal bandwidth, as linearity is typically traded off against bandwidth and power in traditional designs, limiting the dynamic range of amplifiers and other circuits.
Innovation Solution
The implementation of semi-cascoding in current mirror arrangements, which includes transistors configured in a semi-cascoding stage with a two-terminal passive network, reduces nonlinearity by allowing the base/gate voltage of a transistor to swing with the output signal, effectively reducing the signal swing across base-collector junction capacitances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional current mirror designs are used, then the circuit complexity is low, but the linearity and signal bandwidth are limited due to the trade-off between linearity, bandwidth, and power
Solution Approach 1:
The current mirror circuit is segmented into multiple stages: a first current mirror circuit and a second current mirror circuit, each with specific transistors configured to handle different aspects of current mirroring. This segmentation allows optimization of linearity in each stage while managing overall complexity
Solution Approach 2:
The patent introduces dynamic voltage swing capability at the base/gate terminals of transistors Q3 and Q4, allowing them to swing with the output signal. This dynamic behavior reduces the signal swing across base-collector junction capacitances, thereby improving linearity without requiring excessive power or complexity
2Productivity
If traditional current mirror designs are used, then the power consumption is low, but the signal bandwidth is limited
Solution Approach 1:
By enabling dynamic voltage swing at transistor bases/gates rather than holding them at fixed bias voltages, the circuit achieves wider signal bandwidth. The semi-cascoding configuration with capacitive coupling allows the circuit to respond more quickly to signal changes, improving bandwidth without proportionally increasing power consumption
3Manufacturing precision
If the base/gate voltage is held at a fixed bias voltage, then the circuit stability is high, but the linearity deteriorates due to large signal swing across base-collector junction capacitances
Solution Approach 1:
Capacitors are introduced as intermediary elements between the fixed bias voltage sources and the transistor base/gate terminals. These capacitors couple the dynamic signal while blocking the DC bias, allowing the base/gate voltages to swing dynamically without compromising the stability of the bias reference points
Solution Approach 2:
The patent transitions from static bias voltage to dynamic voltage swing at transistor bases/gates. This dynamic approach allows the voltages to follow the output signal, reducing the effective signal swing across base-collector junctions and improving linearity while maintaining circuit stability through proper biasing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly improves linearity by reducing the nonlinear current at the output, allowing for both high linearity and wide signal bandwidth, enhancing the performance of current mirrors in applications requiring high-frequency signal generation.
Implementation Method 1
reducing the signal swing across base-collector junction capacitances
Data Source
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AI summary
An example current mirror arrangement includes a current mirror circuit, configured to receive an input current signal at an input transistor Q1 and output a mirrored signal at an output transistor Q2. The arrangement further includes a semi-cascoding circuit that includes transistors Q3, Q4, and a two-terminal passive network. The transistor Q3 is coupled to, and forms a cascode with, the output transistor Q2. The transistor Q4 is coupled to the transistor Q3. The base/gate of the transistor Q3 is coupled to a bias voltage Vref, and the base/gate of the transistor Q4 is coupled to a bias voltage Vref1 via the two-terminal passive network. Nonlinearity of the output current from such a current mirror arrangement may be reduced by selecting appropriate impedance of the two-terminal passive network and selecting appropriate bias voltages Vref and Vref1.