Semi-Damascene Hardmask Structure for Dielectric-Safe Etching
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Solution Overview
Problem
The existing methods for forming semi-damascene structures in semiconductor devices often result in damage to the intermetal dielectric layer, leading to increased dielectric constant values and time-dependent dielectric breakdown, as well as issues with etch loading and under-etching, which affect the performance and reliability of the semiconductor device.
Innovation Solution
A semi-damascene structure is developed where a dielectric hardmask layer is embedded within the intermetal dielectric layer, preventing direct contact between the metal structure and the intermetal dielectric layer and acting as an etch stop to avoid damage and misalignment, thereby maintaining the integrity of the intermetal dielectric layer and improving etching precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the metal structure is filled in the via hole and extends on the intermetal dielectric layer, then the metal lines can be formed for connection, but the intermetal dielectric layer is damaged at its upper portion, increasing the dielectric constant value and adversely affecting performance
Solution Approach 1:
A hardmask layer is introduced as an intermediary between the metal structure and the intermetal dielectric layer. This hardmask layer prevents direct contact between the metal and the dielectric layer, thereby avoiding damage to the dielectric layer's upper portion and maintaining its dielectric constant value and performance.
2Manufacturing precision
If plasma dry etching is performed to etch the metal structure, then metal lines can be formed, but etch loading occurs on the intermetal dielectric layer, further damaging it and weakening the time-dependent dielectric breakdown voltage
Solution Approach 1:
The hardmask layer serves as a protective intermediary during the plasma dry etching process. It absorbs the etch loading effect, preventing the plasma from directly attacking the intermetal dielectric layer. This maintains the dielectric layer's integrity and preserves its time-dependent dielectric breakdown voltage while still allowing precise etching of the metal lines.
3Manufacturing precision
If the photoresist pattern is used as mask structure to etch the hardmask layer and intermetal dielectric layer, then via holes can be formed, but the process requires multiple layers and steps increasing manufacturing complexity
Solution Approach 1:
The hardmask layer is designed to serve multiple functions: it acts as a mask layer during via hole formation, provides mechanical support during metal filling, and protects the intermetal dielectric layer from damage. This multi-functionality reduces the need for additional separate layers and process steps, thereby simplifying the overall manufacturing process while maintaining via hole formation precision.
Data Source
AI summary
A method of manufacturing a semi-damascene structure of a semiconductor device includes: forming a 1st intermetal dielectric layer; forming a 1st hardmask layer and at least one 1st photoresist pattern on the 1st intermetal dielectric layer; patterning at least one via hole penetrating through the 1st hardmask layer and the 1st intermetal dielectric using the 1st photoresist pattern; removing the 1st photoresist pattern among the 1st photoresist pattern and the 1st hardmask layer; forming a metal structure in the via hole such that the metal structure fills in the vial hole and extends on the 1st hardmask layer; patterning the metal structure to form at least one 1st trench penetrating at least the metal structure at a portion where the metal structure extends on the 1st hardmask layer; and filling the 1st trench with a 2nd inter-metal layer.