Semi-Floating Gate Memory Structure Without Implantation Masks
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Solution Overview
Problem
The existing semi-floating gate memory devices require separate masks for source and drain ion implantation, leading to high fabrication costs.
Innovation Solution
A semi-floating gate memory device with an epitaxial growth structure that eliminates the need for separate source and drain ion implantation masks, featuring a double control gate with a high-K/metal gate and silicon oxide/polysilicon gate, where a control gate epitaxial silicon layer, source region, and drain region are formed through silicon epitaxial growth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate masks are used for source and drain ion implantation, then ion implantation precision is improved, but device complexity and fabrication cost increase
Solution Approach 1:
The patent combines the source and drain ion implantation processes into a single step by forming the gate structure first, then performing ion implantation through the gate. This merging of previously separate processes (source implantation and drain implantation) into one unified process eliminates the need for separate masks while maintaining implantation precision through the gate structure itself acting as the positioning reference.
Solution Approach 2:
The gate structure serves multiple functions: it acts as both the control electrode and as the mask/reference for ion implantation positioning. By making the gate structure multi-functional, the patent eliminates the need for separate dedicated masks for source and drain implantation, thereby reducing fabrication complexity while maintaining precision.
2Manufacturing precision
If separate masks are used for source and drain ion implantation, then ion implantation precision is improved, but fabrication cost increases
Solution Approach 1:
The patent merges separate mask fabrication and application steps into a single process flow where the gate structure itself serves as the positioning reference. This reduction in the number of discrete manufacturing steps directly lowers fabrication costs while preserving implantation precision through the gate's structural definition.
Solution Approach 2:
The patent extracts and eliminates the separate mask components from the fabrication process. By removing the need for dedicated source and drain masks, the patent reduces material costs, process steps, and associated expenses while maintaining precision through the gate structure's inherent positioning capability.
3Object-generated harmful factors
If high-K/metal gate is used to replace oxide/polysilicon gate, then gate leakage current is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent employs a composite gate structure combining high-K dielectric material and metal gate layer. This composite material approach reduces gate leakage current by utilizing the high dielectric constant of HfO2 to achieve lower equivalent oxide thickness while maintaining gate control, and the metal gate provides excellent electrical properties. The integrated formation process through ion implantation helps manage the manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces fabrication costs by eliminating the need for separate ion implantation masks and enables efficient formation of a double control gate semi-floating gate memory device with a high-K/metal gate and silicon oxide/polysilicon gate.
Implementation Method 1
a high-K dielectric layer 112 between the metal gate 113 and the control gate polysilicon layer 111; the high-K dielectric layer 112 is made of HfO2, HfSiO, HfSiON, HfAlO or HfAlON
Implementation Method 2
a control gate epitaxial silicon layer 114, a source region 107 and a drain region 108 are formed by an epitaxial growth structure
Data Source
AI summary
The present application discloses a semi-floating gate memory device, which is a double control gate semi-floating gate memory device with a high-K/metal gate and a silicon oxide/polysilicon gate. A control gate epitaxial silicon layer, a source region and a drain region are formed by an epitaxial growth structure, separate source and drain ion implantation is not needed, the mask required for source and drain ion implantation is saved, and the fabrication cost is low. The present application further discloses a method for fabricating the semi-floating gate memory device.