Semi-insulating Field Plate Structure for Power Semiconductor Devices
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Solution Overview
Problem
The manufacturing of semi-insulating field plates in power semiconductor devices is costly due to the need for additional etching steps, and existing methods either pollute the electric furnace or cause degradation in electrical performance.
Innovation Solution
A thin semi-insulating layer, made of high resistivity materials like titanium nitride, polycrystalline silicon, or amorphous silicon, is deposited between metal electrodes on the surface of the device, with the electrodes penetrating through the layer during annealing, eliminating the need for etching and maintaining electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a semi-insulating field plate is implemented using SIPOS layer deposition before metallization, then uniform electric field distribution is achieved, but an additional etching step is required which increases manufacturing cost
Solution Approach 1:
The patent extracts and eliminates the etching step from the manufacturing process by using a different material (amorphous silicon with specific doping) that allows direct metal deposition without requiring subsequent etching to create contact holes, thereby reducing manufacturing cost while maintaining the field plate function
Solution Approach 2:
The patent changes the material parameters by using amorphous silicon with specific resistivity ranges (10-1000 ohm-cm) and controlled doping concentrations, which allows the material to serve as both the field plate and a material that facilitates direct metal contact without etching, thus resolving the contradiction between reliability and ease of manufacture
2Ease of manufacture
If amorphous silicon layer is deposited after metallization to serve as semi-insulating field plate, then etching step is eliminated, but metal pollution occurs in the electric furnace
Solution Approach 1:
The patent applies preliminary action by depositing the amorphous silicon layer and doping it before metallization, so that the layer is already in its final semi-insulating state when metals are deposited subsequently, eliminating the need for post-metallization deposition and avoiding electric furnace pollution while maintaining process simplicity
3Ease of manufacture
If amorphous silicon layer is deposited before metallization to serve as semi-insulating field plate, then etching step is eliminated, but contact resistance between metal and silicon increases causing degradation of electrical performance
Solution Approach 1:
The patent applies local quality by creating different regions within the amorphous silicon layer: a lightly-doped region (10^16 to 10^18 atoms/cm³) at the metal contact interface to reduce contact resistance, and a heavily-doped region (10^19 to 10^21 atoms/cm³) in the bulk to provide semi-insulating properties, thus achieving both process simplicity and electrical performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs and prevents electrical performance degradation by ensuring uniform electric field distribution without the need for etching, thus enhancing the breakdown voltage of power semiconductor devices.
Implementation Method 1
a thin semi-insulating layer, made of high resistivity materials like titanium nitride, polycrystalline silicon, or amorphous silicon, is deposited between metal electrodes
Implementation Method 2
with the electrodes penetrating through the layer during annealing
Data Source
AI summary
A structure and a manufacturing method of a power semiconductor device are provided. A structure of thin semi-insulating field plates (32, 33, 34) located between metal electrodes (21, 22, 23) at the surface of the power semiconductor device is provided. The thin semi-insulating field plates (32, 33, 34) are formed by depositing before metallization and annealing after the metallization. The present invention can be used in lateral power semiconductor devices and vertical power semiconductor devices.