Semi-Network Memory Architecture for Channel Bottleneck Resolution
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Solution Overview
Problem
In multi-channel memory systems, existing architectures face inefficiencies in data transmission due to channel bottlenecks, where read requests from multiple memory devices on the same channel must wait for data to be cleared before transmitting, leading to increased latency and reduced scalability.
Innovation Solution
Implementing a semi-network structure where memory devices can output data to different channels using interconnections, allowing parallel data transmission from memory devices on the same channel by including demultiplexers and additional I/O pads, enabling data to be routed through alternative channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If multiple memory devices on the same channel transmit data sequentially, then channel capacity is maintained, but read latency increases and channel utilization decreases
Solution Approach 1:
The patent segments the data transmission path by introducing inter-channel interconnections that allow memory devices on different channels to communicate with each other. This creates alternative data routes that bypass the primary channel bottleneck, enabling parallel data paths and reducing read latency while improving channel utilization.
Solution Approach 2:
The patent introduces inter-channel interconnections as intermediary pathways between channels. These interconnections act as mediators that allow data to be routed from memory devices on one channel to memory devices on other channels, eliminating the sequential transmission constraint and reducing latency.
2Adaptability or versatility
If strict channel assignment is enforced, then data transmission is simple, but channel scalability is limited and idle channels cannot be utilized
Solution Approach 1:
The patent makes memory devices multi-functional by enabling them to operate in both read and write modes regardless of their assigned channel. Memory devices can be dynamically assigned to different channels based on operational needs, allowing flexible channel utilization and improved scalability without increasing routing complexity.
Solution Approach 2:
The patent introduces dynamic channel assignment where memory devices can switch between channels based on real-time operational requirements. This dynamic flexibility allows the system to optimize performance by routing data through available channels, improving scalability while maintaining manageable complexity through software-controlled routing.
3Productivity
If read requests are processed sequentially on the same channel, then channel infrastructure is simple, but system throughput is reduced
Solution Approach 1:
The patent merges multiple channels into a unified data transmission network by introducing inter-channel interconnections. This merging allows read requests to be distributed across multiple channels simultaneously, increasing system throughput. The interconnection structure is designed to enable parallel data paths while maintaining manageable complexity through standardized connection protocols.
Data Source
AI summary
A memory system includes a first plurality of nonvolatile memory devices of a first channel of the memory system, the first plurality of memory devices each being connected to a first communications bus; a second plurality of nonvolatile memory devices of a second channel of the memory system, the second plurality of memory devices each being connected to a second communications bus, and a first interconnection between a first memory device and a second memory device, the first memory device being a memory device from among the first plurality of nonvolatile memory devices, the second memory device being a memory device from among the second plurality of nonvolatile memory devices.