Semi-Parallel LDPC Decoder Architecture for Reconfigurable Throughput
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Solution Overview
Problem
Existing LDPC code decoder hardware faces challenges in managing message passing during iterative belief propagation, leading to high complexity and time requirements due to the need for look-up tables, log likelihood ratio computations, and storage, making it inefficient for large block lengths and reconfigurability.
Innovation Solution
A semi-parallel processing method is introduced, utilizing a variable node bank and check node computation units with a switching network to transfer and compute LogLikelihood Ratio values, eliminating the need for look-up tables and enabling reconfigurability by using the Min-Sum algorithm with a compensation factor to reduce bit and frame error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fully parallel decoding architecture is used, then decoding throughput is improved, but hardware area and implementation complexity increase significantly
Solution Approach 1:
The decoder is segmented into multiple processing units that operate in parallel on different subsets of the code block. Each processing unit handles a portion of the variable nodes and check nodes, allowing the system to achieve high throughput while keeping individual unit complexity manageable. The code block is divided into segments that can be processed simultaneously by different units.
Solution Approach 2:
The architecture introduces a temporal dimension by using iterative processing with multiple passes through the data. Instead of processing all nodes simultaneously in a single parallel layer, the system uses multiple sequential iterations where each iteration processes a subset of nodes, effectively trading some parallelism for iterative refinement while reducing peak hardware requirements.
2Measurement precision
If look-up tables and log likelihood ratio computations are used, then decoding accuracy is improved, but computational complexity and time requirements increase
Solution Approach 1:
The system changes the parameter representation by working directly with soft bit values and simplified likelihood ratios rather than full log likelihood ratios. This parameter transformation reduces the computational burden while maintaining sufficient decoding accuracy. The soft bit values are updated using simplified update rules that avoid complex logarithmic computations.
Solution Approach 2:
Instead of using expensive and complex look-up tables, the system employs simple arithmetic operations and lightweight computational structures that can be rapidly executed. The computational approach uses basic mathematical operations that are computationally cheap and can be performed quickly without requiring large memory structures or complex circuitry.
3Ease of manufacture
If fixed hardware design is used, then implementation is simplified, but reconfigurability for different block lengths and code rates is lost
Solution Approach 1:
The hardware design incorporates dynamic elements that allow reconfiguration for different code parameters. The processing units can be dynamically allocated and configured to handle different block lengths and code rates by adjusting the connectivity patterns and processing schedules. This dynamic reconfiguration capability is achieved through programmable interconnects and configurable processing pipelines.
Solution Approach 2:
The processing units are designed with universal functionality to handle multiple code types and parameters. Each processing unit can be configured to work with different parity check matrices and code rates, making the hardware versatile. The same basic unit structure serves multiple functions by changing its operational parameters and connectivity rather than requiring dedicated hardware for each code configuration.
4Measurement precision
If more memory blocks are used to store messages, then message passing accuracy is improved, but memory requirements and area increase
Solution Approach 1:
The message storage is segmented into smaller distributed memory structures associated with each processing unit rather than using large centralized memory blocks. Each processing unit has its own local memory for storing incoming and outgoing messages, which reduces the peak memory requirements. The segmentation allows message passing to be performed with sufficient accuracy using smaller, more manageable memory structures.
Data Source
AI summary
An error correction system for decoding transmitted data in multichannels is disclosed. The system uses low density parity check nodes. A method of error correction using LDPC is also disclosed.