Semi-polar Modulator Bandwidth Reduction
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Solution Overview
Problem
Polar transmitters face challenges in wider band radio systems like LTE due to higher bandwidth requirements for phase and amplitude modulation signals, difficulty in generating wide linear tuning ranges, and stringent timing alignment needs, which affect Adjacent Channel Leakage Ratio (ACLR) and Error Vector Magnitude (EVM) performance.
Innovation Solution
A modulation processor with a first processing stage that generates a phase signal and reduces the bandwidth of a frequency signal, and a second processing stage that retards the phase of the modulation signal by an integral of the first output signal, producing output signals suitable for polar architecture, enabling reduced bandwidth and improved noise performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If polar modulation is used in LTE, then power efficiency is improved, but bandwidth requirements for phase and amplitude signals become excessively high
Solution Approach 1:
The modulation signal is segmented into in-phase (I) and quadrature (Q) components, which are processed separately through individual DACs and filtering paths. This segmentation allows each component to be optimized independently, reducing the overall bandwidth requirements compared to direct polar modulation while maintaining power efficiency benefits.
Solution Approach 2:
The patent transitions from direct polar coordinates (amplitude and phase) to a two-dimensional Cartesian representation (I and Q components). This dimensional transformation allows the signal to be processed in a way that reduces bandwidth requirements while achieving similar power efficiency through digital signal processing optimization.
2Reliability
If bandwidth of phase and amplitude signals is reduced, then ACLR and EVM performance is improved, but the composite signal bandwidth becomes larger than the modulating signals
Solution Approach 1:
The patent employs dynamic filtering where the cutoff frequencies of the low-pass filters for I and Q components are optimized based on the specific LTE signal characteristics and bandwidth requirements. This dynamic adjustment allows the system to achieve optimal ACLR and EVM performance while minimizing the composite signal bandwidth expansion effect.
Solution Approach 2:
The patent changes key parameters including the filtering characteristics, DAC resolution, and sampling rates to optimize the balance between modulating signal bandwidth and composite signal bandwidth. By carefully selecting these parameters, the system achieves improved ACLR and EVM without excessive bandwidth expansion.
3Adaptability or versatility
If high modulation bandwidth is used in LTE, then frequency division duplex performance is improved, but timing alignment requirements become extremely stringent
Solution Approach 1:
The patent replaces mechanical/physical timing alignment mechanisms with digital signal processing techniques. Through digital filtering and synchronization algorithms applied to the I and Q components, the system achieves the required timing alignment precision without relying on physical synchronization hardware, thereby reducing the stringency of timing requirements while maintaining FDD performance.
4Speed
If wide linear tuning range is generated for phase locked loop, then frequency deviation capability is improved, but available tuning range for multiple bands is reduced
Solution Approach 1:
The patent designs the phase-locked loop and frequency synthesis system to serve multiple functions: it provides the required wide frequency deviation for modulation while simultaneously supporting tuning across multiple frequency bands. This is achieved through a unified frequency synthesis architecture that can operate in both modes, eliminating the trade-off between deviation capability and multi-band support.
Data Source
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AI summary
A modulation processor (500) comprises a first processing stage (110) and a second processing stage (120). The first processing stage (110) comprises a phase generation stage (117) arranged to generate a phase signal (PM) indicative of a phase of a modulation signal (S), a differentiation stage (118) arranged to generate a frequency signal (FM) by differentiating the phase signal (PM), and a first bandwidth reduction stage (113) arranged to generate a first output signal (FM_LP) by reducing a bandwidth of the frequency signal (FM). The second processing stage (120) is arranged to generate a second output signal (AM*) proportional to the modulation signal (S) with its phase retarded by an angle equal to an integral of the first output signal (FM_LP).