Semi-Static Inverting Latch for Low-Power Wide-Frequency Operation
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Solution Overview
Problem
High-performance computing chips, particularly those used in digital currency processing, face challenges in power consumption, operational speed, and area due to the need for a large number of latches for repetitive logical calculations.
Innovation Solution
A semi-static latch with an inverted output is introduced, featuring an input stage, an output stage, an intermediate node, and a feedback stage that assumes logic-high, logic-low, and high-impedance states, allowing the latch to operate at various frequencies without minimum frequency limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a large number of latches are used for repetitive logical calculations in digital currency processing, then computational capability is improved, but power consumption increases
Solution Approach 1:
The latch circuit employs dynamic operation modes where the feedback stage can be selectively enabled or disabled based on operational requirements. The circuit transitions between static and dynamic states, allowing it to maintain data during clock periods while consuming minimal power when full switching activity is not required. This dynamic behavior reduces average power consumption while maintaining computational capability.
Solution Approach 2:
The latch circuit allows adjustment of operational parameters including clock frequency ranges (from low to high frequencies) and power consumption levels. By changing the operating state of the feedback stage and adjusting clock signal characteristics, the circuit can adapt its power consumption to match the computational workload, enabling efficient operation across different performance requirements.
2Speed
If traditional latch circuits are used to meet minimum frequency requirements, then operational speed is improved, but power consumption increases due to continuous switching
Solution Approach 1:
The latch circuit utilizes periodic clock signals to control the feedback stage, enabling it to operate only during specific phases of the clock cycle. During certain periods, the feedback is active to maintain data; during other periods, it enters a high-impedance state to minimize power consumption. This periodic activation aligns switching activity with computational needs rather than continuous operation.
Solution Approach 2:
The circuit dynamically adjusts its operational state based on clock frequency and data hold requirements. At low frequencies, the feedback stage remains active longer to ensure data stability. At high frequencies, it switches more rapidly and spends more time in low-power states. This dynamic adaptation allows the circuit to maintain minimum frequency requirements while minimizing unnecessary switching power consumption.
3Use of energy by moving object
If the latch operates at low frequencies to reduce power consumption, then power efficiency is improved, but operational speed decreases
Solution Approach 1:
The latch circuit enables flexible parameter adjustment, allowing it to operate across a wide frequency range from low to high frequencies. By changing operational parameters such as feedback stage activation and clock signal characteristics, the circuit can adapt to different speed requirements while maintaining power efficiency. This parameter flexibility resolves the fixed trade-off between speed and power consumption.
Solution Approach 2:
The latch circuit is designed to perform multiple functions across different operational modes: it can operate as a high-speed latch when frequency is not critical, as a low-power latch when energy efficiency is prioritized, and adapt to intermediate states. This multi-functionality allows the same circuit to serve diverse computational needs without being constrained to a single speed-power trade-off point.
4Reliability
If feedback stage is continuously active to maintain data stability, then reliability is improved, but power consumption increases
Solution Approach 1:
The feedback stage operates periodically rather than continuously, activating only during clock periods when data stability is required and entering high-impedance states during periods when data hold is maintained by circuit capacitance. This periodic operation maintains data reliability while significantly reducing the average power consumption compared to continuous feedback activation.
Solution Approach 2:
The feedback stage is extracted from continuous operation and selectively engaged only when needed for data stability. The circuit design allows the feedback path to be removed or disabled during periods when data hold does not require active feedback, separating the reliability function from continuous power consumption and enabling reliability only when necessary.
Data Source
AI summary
The present disclosure relates to a latch, a processor including the latch, and a computing apparatus. A latch with an inverted output is provided, including: an input stage configured to receive a latch input; an output stage configured to output a latch output; an intermediate node disposed between an output of the input stage and an input of the output stage, wherein the output stage is configured to receive a signal at the intermediate node as an input; and a feedback stage configured to receive the latch output and provide a feedback to the intermediate node, wherein feedback stage assumes a logic-high state, a logic-low state, and a high-impedance state, wherein the latch output is inverted from the latch input.