Semi-Circle Select Gate Memory Hole Erase Speed Compensation
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Solution Overview
Problem
Semi-circle drain side select gate (SC-SGD) memory technology faces inefficiencies due to improper cutting of memory holes, leading to slower erase speeds compared to full circle drain side select gate (FC-SGD), which can render SC-SGD unusable and cause reliability issues during data storage.
Innovation Solution
Programming select gates of memory holes with different threshold voltages to match the erase speed of FC-SGD, either by increasing the threshold voltage for SC-SGD or decreasing it for FC-SGD, allowing both to achieve similar erase speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If memory holes are cut to form semi-circle drain side select gate (SC-SGD), then die size is reduced, but erase speed becomes slower compared to full circle drain side select gate (FC-SGD)
Solution Approach 1:
The patent applies parameter changes by adjusting the threshold voltage of select gates to compensate for the slower erase speed of SC-SGD. Specifically, FC-SGD select gates are programmed to a lower threshold voltage while SC-SGD select gates are programmed to a higher threshold voltage, which balances the erase speeds of both memory hole types and resolves the speed disadvantage of the reduced-die-size SC-SGD structure
2Area of stationary object
If etching technology is used to cut memory holes for SC-SGD, then die size is reduced, but improper cutting can render memory holes useless
Solution Approach 1:
The patent applies local quality by implementing different threshold voltage programming strategies for different types of memory holes based on their geometric characteristics. FC-SGD memory holes receive one threshold voltage programming treatment while SC-SGD memory holes receive a different treatment, allowing each type to be optimized for its specific structure and ensuring reliable functionality despite variations in cutting quality
3Speed
If different threshold voltages are applied to FC-SGD and SC-SGD, then erase speeds are equalized, but programming complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the memory array into distinct regions containing FC-SGD and SC-SGD memory holes, and applying different threshold voltage programming parameters to each region. This segmented approach allows systematic management of the programming process, where each segment is handled with its optimized parameters, making the overall complexity manageable through structured organization
Data Source
AI summary
Non-volatile memory systems are disclosed. The memory systems include rows of memory holes FC-SGD and SC-SGD, the latter of which may be created by a SHE cutting operation. The SC-SGD include erase speeds slower than those of FC-SGD. In order to overcome the erase speed disparities, SC-SGD are programmed to a higher Vt as compared to FC-SGD. By programming SC-SGD to a higher Vt, the erase speed increases and matches the erase speed of FC-SGD. Further, different SC-SGDs are cut to different amounts, creating different erase speeds among SC-SGD. SC-SGDs with a greater degree/amount of cut have slower erase speeds as compared to SC-SGDs with a lesser degree/amount of cut. However, verify levels among SC-SGDs can differ to produce SC-SGDs with Vt's such that their erase speeds match with each other as well as with FC-SGD.