Semiconductive Structure With Trench Width Variation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As dynamic random access memory (DRAM) units become more highly integrated and miniaturized, the reduced pitch of buried word lines increases parasitic capacitance, leading to the row hammer effect, where electrons accumulate on buried word lines, causing data loss in adjacent drain regions.
Innovation Solution
A semiconductive structure is designed with specific trench widths and layers, including silicon oxide and nitride layers, to reduce parasitic capacitance by forming a word line that overlaps the nitride layer in a way that minimizes capacitance, using a substrate with memory and peripheral regions and carefully controlled trench formations and layer deposition processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the pitch of buried word lines is reduced to increase integration density, then the integration density is improved, but parasitic capacitance increases leading to row hammer effect
Solution Approach 1:
The patent applies different trench widths at different locations: a first trench width in the memory cell region, a second trench width in the passing gate region (wider than first), and a third trench width in the peripheral region (wider than second). This local variation in trench dimensions reduces parasitic capacitance specifically at passing gate regions where the row hammer effect occurs, while maintaining tight pitch in memory cell regions for high integration density.
Solution Approach 2:
The substrate is divided into different regions (memory cell region, passing gate region, peripheral region) with different trench configurations. This segmentation allows optimized trench widths for each functional region, reducing parasitic capacitance at critical passing gate locations without compromising overall integration density.
2Object-affected harmful factors
If multiple trench isolation layers are formed to reduce parasitic capacitance, then parasitic capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent forms trench isolation layers in a specific sequence: first forming the first trench isolation layer, then the second trench isolation layer, and finally the third trench isolation layer. This preliminary ordering of operations simplifies the manufacturing process by establishing a clear fabrication sequence that reduces parasitic capacitance without requiring complex simultaneous operations or rework.
Solution Approach 2:
The patent uses nested trench structures where the first trench is formed within the memory cell region, the second trench (wider) encompasses the passing gate region, and the third trench (widest) is in the peripheral region. These nested isolation structures reduce parasitic capacitance through multiple layers while following a systematic fabrication approach that manages manufacturing complexity.
Data Source
AI summary
A method of fabricating a semiconductive structure with a word line includes providing a substrate including a memory cell region and a peripheral region. A first trench and second trench are formed within the memory cell region, and a third trench is formed within the peripheral region. A width of the first trench is smaller than the second trench, and the width of the second trench is smaller than the third trench. A first silicon oxide layer fills up the first trench. A silicon nitride layer fills up the second trench and covers the third trench. A second silicon oxide layer is formed in the third trench. Part of the substrate within the memory cell region, part of the first silicon oxide layer, and part of the silicon nitride layer are removed to form a word line trench. Finally, a word line is formed in the word line trench.