Semiconductor Conductive Features with 2D Material Layers

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Solution Overview

Problem

As semiconductor devices continue to shrink in size, the complexity of processing and manufacturing increases, particularly due to rising resistance issues in copper-based connecting structures during front-end-of-line (FEOL), middle-end-of-line (MEOL), and back-end-of-line (BEOL) processes in IC fabrication.

Innovation Solution

Incorporating two-dimensional (2D) materials between three-dimensional (3D) material layers in semiconductor structures to form conductive features, such as MEOL and BEOL connecting structures, which reduces resistance and maintains mechanical strength, enabling efficient scaling down of ICs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If copper-based connecting structures are used in FEOL, MEOL, and BEOL processes, then electrical conductivity is maintained, but resistance increases as device size decreases

Engineering Contradiction:
Improveelectrical conductivityVSAvoidresistance
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent employs a composite material structure consisting of a copper seed layer combined with a copper barrier layer. This composite structure maintains the electrical conductivity benefits of copper while the barrier layer prevents diffusion and reduces resistance issues in scaled-down devices, resolving the contradiction between maintaining conductivity and reducing resistance in miniaturized connecting structures.

Inventive Principle:
Principle #40Composite materials

2Productivity

If feature sizes continue to decrease to increase functional density, then production efficiency improves and costs decrease, but fabrication process complexity and difficulty increase

Engineering Contradiction:
Improvefunctional densityVSAvoidfabrication process complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the connecting structure into distinct functional layers: a copper seed layer for electrical conductivity and a copper barrier layer for diffusion prevention. This segmentation allows each layer to be optimized independently for its specific function, enabling continued scaling to increase functional density while managing fabrication complexity through modular layer design.

Inventive Principle:
Principle #1Segmentation

3Productivity

If feature sizes continue to decrease to increase functional density, then production efficiency improves and costs decrease, but manufacturing precision requirements increase

Engineering Contradiction:
Improvefunctional densityVSAvoidfabrication precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent applies local quality by providing different material properties in different regions of the connecting structure. The copper seed layer provides electrical conductivity where needed, while the copper barrier layer provides diffusion prevention in critical regions. This localized functional differentiation enables precise control over electrical and structural properties, allowing continued scaling while maintaining manufacturing precision.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11682616B2Semiconductor structure and method for forming the same
Publication Date: 2023.06.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11682616B2 patent drawing
  • US11682616B2 patent drawing
  • US11682616B2 patent drawing

AI summary

A semiconductor structure includes a substrate, a plurality of conductive features disposed over the substrate, and an isolation structure between conductive features and separating the conductive features from each other. Each of the conductive features includes a first metal layer and a 2D material layer. Another semiconductor structure includes a first conductive feature, a dielectric structure over the first conductive feature, a second conductive feature in the dielectric structure and coupled to the first conductive feature, and a conductive line over and coupled to the second conductive feature. In some embodiments, the conductive line includes a first 3D material layer, a first 2D material layer, and a second 3D material layer. The first 2D material layer is disposed between the first 3D material layer and the second 3D material layer.