3D Inductor in Semiconductor Package with Metal Bars
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Solution Overview
Problem
The challenge in semiconductor devices is to achieve a high quality factor (Q-factor) for inductors while minimizing space, as traditional 2D inductors require large coil areas and 3D inductors with tall Cu pillars or TGV/TSV are difficult to manufacture and suffer from skin effect issues.
Innovation Solution
The semiconductor device incorporates a carrier with insulation layers and conductive metal bars forming interconnection structures that function as a 3D inductor, providing high Q-factor and reduced package size through a combination of top-side and bottom-side metal bars and conductive layers, which are connected to a capacitor element, allowing for efficient current distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a 2D inductor with large coil area is used to achieve high Q-factor, then the Q-factor is improved, but the device occupies huge space on the carrier
Solution Approach 1:
The patent transitions from a 2D planar inductor design to a 3D vertical structure by forming conductive pillars extending through multiple insulation layers. This dimensional change allows the inductor to achieve high Q-factor through increased effective area in the vertical dimension while maintaining a compact footprint on the carrier surface.
2Reliability
If tall Cu pillars or TGV/TSV with high aspect ratio are used to create 3D inductor, then the Q-factor is improved, but the manufacturing difficulty increases significantly
Solution Approach 1:
The patent divides the inductor structure into multiple discrete conductive pillars distributed across several insulation layers. Each pillar is formed through separate through-holes in the insulation layers, allowing independent formation and reducing the aspect ratio requirements compared to a single tall pillar. This segmentation makes the structure more manufacturable while maintaining the 3D configuration for high Q-factor.
3Reliability
If tall Cu pillars or TGV/TSV are used in 3D inductor, then the Q-factor is improved, but the majority of the structure becomes redundant due to skin effect
Solution Approach 1:
The patent segments the conductive path into multiple shorter pillars distributed across different insulation layers rather than using a single tall pillar. This segmentation reduces the depth of each conductive element, minimizing the portion of material affected by skin effect and reducing redundant material while maintaining the overall 3D inductor functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves a high Q-factor comparable to 3D inductors while maintaining a compact form factor, overcoming manufacturing challenges and skin effect limitations, and is cost-effective for both 2.5D and 3D IC packages.
Implementation Method 1
the majority of a Cu pillar or TGV/TSV is redundant due to the tendency of an alternating current (AC) to become distributed within a conductor such that the current density is largest near the surface of the conductor, and decreases with greater depths in the conductor (e.g., a Skin effect)
Implementation Method 2
The capacitor element is in the first insulation layer, the capacitor element including a top electrode and a bottom electrode
Data Source
AI summary
A semiconductor device package includes a carrier, a first insulation layer, a capacitor element, a plurality of interconnection structures, a plurality of substantially parallel top-side metal bars, and a plurality of substantially parallel bottom-side metal bars. The first insulation layer is on the carrier and has a first surface and a second surface adjacent to the carrier and opposite to the first surface, the first insulation layer defining a plurality of through holes. The capacitor element is in the first insulation layer, the capacitor element including a top electrode and a bottom electrode. The plurality of interconnection structures are within the through holes and formed as conductive through holes. The plurality of substantially parallel top-side metal bars are on the first surface of the first insulation layer. The plurality of substantially parallel bottom-side metal bars are on the second surface of the first insulation layer.