3D Inductor Structure for Semiconductor Device Miniaturization
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Solution Overview
Problem
Conventional semiconductor devices with integrated inductors face challenges in microminiaturization due to the large space occupied by spiral inductor structures on insulation layers, which hinder compact design and efficient layout.
Innovation Solution
The implementation of a three-dimensional inductor structure using conductive vias that connect redistribution layers on opposite sides of a substrate, reducing the surface area occupied by the inductor and enabling a more compact semiconductor device design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a spiral inductor structure is disposed on the surface of an insulation layer, then the inductor can be integrated into the semiconductor device, but the spiral structure occupies a large space
Solution Approach 1:
The patent transitions from a two-dimensional spiral inductor structure on the surface to a three-dimensional structure utilizing conductive vias that extend through the substrate. The inductor is formed by connecting conductive segments at different depths and locations, including first conductive segments in the substrate, second conductive segments on the surface, and third conductive segments in another substrate, thereby reducing the surface area occupied while maintaining inductance functionality
Solution Approach 2:
The inductor structure is nested within the substrate by forming conductive vias that extend through the substrate and connecting conductive segments at multiple levels. The first conductive segments are embedded in the substrate, the second conductive segments are formed on the surface, and the third conductive segments are embedded in another substrate, creating a compact nested configuration that reduces overall device footprint
Data Source
AI summary
A semiconductor device includes a substrate, at least one integrated passive device, a first redistribution layer, a second redistribution layer, and conductive vias. The at least one integrated passive device includes at least one capacitor disposed adjacent to a first surface of the substrate. The first redistribution layer is disposed adjacent to the first surface of the substrate. The second redistribution layer is disposed adjacent to a second surface of the substrate. The conductive vias extend through the substrate, and electrically connect the first redistribution layer and the second redistribution layer.