Semiconductor Access Control Circuit for Parity Error Blocking
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Solution Overview
Problem
Semiconductor devices face challenges in verifying the proper logic of control signals, such as command and address signals, leading to potential parity errors that can result in erroneous operations, data destruction, and overwriting of incorrect data.
Innovation Solution
Incorporating an access control circuit with a verification circuit that checks the parity of command and address signals, converting erroneous commands into a DESEL or NOP command to prevent access to the memory cell array, thereby maintaining data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a verification circuit is added to check the parity of command and address signals, then data integrity and reliability are improved, but device complexity increases
Solution Approach 1:
The verification circuit performs parity checking on command and address signals before they are executed by the memory system. By conducting the verification in advance (prior to memory access operations), the system can detect errors early and prevent erroneous operations, thereby improving data integrity without requiring complex post-processing mechanisms
Solution Approach 2:
The verification circuit acts as an intermediary component between the signal input and the memory execution units. It receives command and address signals, performs parity verification, and only allows properly verified signals to proceed to the memory access circuits. This intermediary function isolates the complexity of error detection from the core memory operations
2Object-affected harmful factors
If erroneous commands are converted to DESEL or NOP commands to prevent access, then harmful effects are reduced, but loss of time occurs due to command conversion and verification
Solution Approach 1:
When a parity error is detected in a command or address signal, the verification circuit converts the erroneous command into a DESEL (deselect) or NOP (no operation) command. This conversion transforms a potentially harmful error into a benign no-operation state, preventing data destruction while maintaining system operation. The harmful error signal is thus converted into a beneficial protective action
Solution Approach 2:
The verification circuit performs rapid parity checking that allows the system to quickly identify and skip erroneous commands. By using simple parity bit comparison, the verification can be completed in minimal time, allowing the system to rapidly detect errors and proceed with corrected commands without significant time penalty
Data Source
AI summary
Disclosed herein is a semiconductor device that includes an access control circuit generating an internal command based on a verification result signal and an external command. The external command indicates at least one of a first command that enables the access control circuit to access a first circuit and a second command that enables the access control circuit not to access the first circuit or enables the access control circuit to maintain a current state of the first circuit. The access control circuit, when the verification result signal indicates a first logic level, generates the internal command based on the external command. The access control circuit, when the verification result signal indicates a second logic level, generates the internal command that corresponds to a second command even if the external command indicates a first command.