Semiconductor Active Contacts With Trench Etch Stop For Stability
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Solution Overview
Problem
As semiconductor devices scale down, it becomes challenging to maintain capacitance and electrical stability between contacts, particularly due to the increasing complexity of three-dimensional channel structures.
Innovation Solution
The semiconductor device incorporates a substrate with an active pattern and multiple gate structures, featuring a gate capping pattern, source/drain pattern, lower and upper active contacts, a trench exposing the lower active contact, and an etching stop film to enhance contact reliability and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the pitch size of the semiconductor device is decreased to increase device density, then productivity is improved, but electrical stability and capacitance control between contacts deteriorate
Solution Approach 1:
The patent introduces a three-dimensional channel structure (fin or nanowire) that extends vertically from the substrate, transforming the traditional two-dimensional channel into a multi-dimensional structure. This allows the device to achieve higher effective channel area and improved current control without proportionally reducing the lateral pitch between contacts, thereby maintaining electrical stability while increasing device density.
Solution Approach 2:
The patent employs a nested contact structure with an upper active contact and a lower active contact positioned at different vertical levels. The lower active contact is embedded within the substrate or deep in the active region, while the upper active contact is positioned closer to the surface. This nested arrangement allows contacts to be stacked vertically, effectively increasing device density without requiring proportional reduction in lateral spacing, thus preserving electrical stability and capacitance characteristics.
2Reliability
If the gate length is increased to improve current control capability, then electrical stability is improved, but device area increases reducing productivity
Solution Approach 1:
The patent utilizes a three-dimensional channel structure (fin or nanowire) that extends vertically, providing enhanced gate control over the channel current without requiring an increase in lateral gate length. The vertical extension of the channel allows the gate to control current through a larger effective area while maintaining a compact lateral footprint, thereby improving current control capability without sacrificing device density.
Data Source
AI summary
Semiconductor devices having improved performance and reliability. For example, a semiconductor device may include a substrate, an active pattern extending in a first direction, on the substrate, a plurality of gate structures on the active pattern, each including a gate electrode that crosses the active pattern. A lower active contact may be connected to a source/drain pattern. A trench may expose the lower active contact, and a width of a bottom surface of the trench in the first direction may be greater than a width of an upper surface of the lower active contact in the first direction. An etching stop film may be along the bottom surface of the trench and side walls of the trench, and have an uppermost surface coplanar with an upper surface of an upper active contact that extends through the etching stop film and is connected to the lower active contact.