Semiconductor Active Fins With Segmented Trench Isolation
Solution Overview
Problem
The short channel effect in field effect transistors (FETs) remains a challenge in semiconductor devices, despite advancements in fabrication processes, and existing fin FETs with 3D spatial structures do not fully address this issue, leading to reliability and integrity concerns.
Innovation Solution
A semiconductor device design featuring first and second memory cell regions with active bases and fins, shallow and deep trench isolations, and a gate electrode structure that includes a gate insulating film and spacers, where the active bases are wider than the fins, and the memory cell regions share active bases to minimize unnecessary regions and enhance miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional FET structures are used, then fabrication processes can be simplified, but short channel effects occur leading to reliability issues
Solution Approach 1:
The isolation structure is segmented into two distinct levels: shallow trench isolation at the first level and deep trench isolation at the second level. This segmentation allows each trench type to perform specific functions - the shallow trench provides basic isolation while the deep trench specifically addresses short channel effects, thereby improving reliability without requiring complete redesign of the fabrication process
Solution Approach 2:
The patent introduces a vertical dimension to the trench isolation structure by forming deep trenches that extend deeper into the substrate than conventional shallow trenches. This dimensional extension creates multiple isolation levels that effectively suppress short channel effects while maintaining compatibility with existing fabrication methodologies
2Area of moving object
If fin width is reduced to increase transistor density, then device miniaturization is achieved, but short channel effects worsen
Solution Approach 1:
The patent transitions from two-dimensional planar isolation to three-dimensional multi-level trench isolation. By forming deep trenches that extend vertically deeper into the substrate, the isolation structure gains an additional dimensional capability to control electric fields and suppress short channel effects even when fin width is reduced for higher density
3Reliability
If active base width is increased to improve transistor performance, then device area increases, but fabrication complexity increases
Solution Approach 1:
The isolation structure is divided into shallow and deep trench segments, each with controlled depth. This segmentation allows the active base width to be increased for improved performance while the trench depths are independently controlled through separate etching processes, managing manufacturing precision requirements
Data Source
AI summary
A semiconductor device includes first and second memory cell regions adjacent to each other on a substrate. At least one active base and a shallow trench isolation may be sequentially laminated at a boundary between the first and second memory cell regions. First and second active fins are formed on respective sides of the shallow trench isolation, and the first and second active fins projecting from the active base. At least one deep trench isolation is formed on one side of the active base.