Semiconductor Active Patterns via Insulating Spacer Self-Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In highly integrated semiconductor devices, the reduction of active pattern widths and distances between them leads to challenges in maintaining electrical isolation and increasing density, often resulting in voids or seams in the isolation layer, which can affect device reliability and performance.
Innovation Solution
A method involving the formation of first and second active patterns on a substrate with selective epitaxial growth, where insulating spacers are used to create a narrow trench and subsequent epitaxial growth forms second active patterns, reducing voids or seams in the isolation layer, and an insulation pattern fills the openings between them.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the width of active patterns and distances between them are reduced to increase integration density, then the integration density increases, but voids or seams form in the isolation layer reducing reliability
Solution Approach 1:
The isolation layer formation is segmented into multiple steps: first forming a preliminary isolation layer, then forming insulating spacers on sidewalls, and finally performing selective epitaxial growth to fill gaps. This segmentation allows each step to address specific requirements, preventing void formation while maintaining high integration density.
Solution Approach 2:
The preliminary isolation layer is formed in advance before the insulating spacers and selective epitaxial growth. This preliminary action provides a foundation that prevents void formation during subsequent processing, ensuring isolation layer quality even when active pattern widths are reduced.
2Productivity
If the width of active patterns is reduced to increase density, then the integration density increases, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
Insulating spacers are introduced as intermediary structures between the active patterns. These spacers are formed with precise width control through atomic layer deposition (ALD), serving as a mediator that defines the final active pattern width indirectly, thereby improving manufacturing precision.
Solution Approach 2:
The patent replaces traditional photolithography-based width definition with a spacer-based self-aligned approach. Instead of directly patterning the active patterns with photolithography, the width is defined by the insulating spacers formed through ALD, which offers superior precision and control.
3Reliability
If insulating spacers are formed to maintain isolation, then electrical isolation is improved, but the process complexity increases
Solution Approach 1:
The insulating spacers serve multiple functions: they provide electrical isolation between active patterns, define the width of the second preliminary active patterns through self-alignment, and prevent void formation in the isolation layer. This multi-functionality reduces the need for separate process steps, thereby managing complexity.
Solution Approach 2:
The formation of insulating spacers and the definition of active pattern widths are merged into a single self-aligned process. The spacers are formed conformally on the sidewalls, and their width automatically defines the active pattern dimensions, combining multiple functions into one operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for increased aspect ratios of active patterns while maintaining electrical isolation, enhancing the reliability and integration density of semiconductor devices by reducing voids and seams in the isolation layer.
Implementation Method 1
performing a selective epitaxial growth (SEG) process using a portion of the substrate exposed by the second trench as a seed to form a second preliminary active pattern in the second trench
Data Source
AI summary
A method of forming patterns of a semiconductor device, including partially etching an upper portion of a substrate to form first preliminary active patterns and a first trench, each of the first preliminary active patterns having a first width, and the first trench having a second width of about 2 to 3 times the first width; forming an insulating spacer on each sidewall of the first trench to form a second trench having the first width; forming a second preliminary active pattern in the second trench, the second preliminary active pattern having the first width; partially etching the first and second preliminary active patterns to form a plurality of first active patterns and a plurality of second active patterns and an opening between the plurality of first and second active patterns; and forming an insulation pattern to fill the opening.