Semiconductor Active Pillars With Auxiliary Conductive Lines
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Solution Overview
Problem
Current semiconductor manufacturing processes for forming fine patterns in three-dimensional electronic structures, such as vertical MOS transistors, face challenges in increasing integration density while avoiding issues like short-channel effects and requiring expensive photolithography processes.
Innovation Solution
The semiconductor device design includes a semiconductor substrate with active pillars defined by trenches, auxiliary and main conductive lines, and impurity regions, where the conductive lines are strategically placed to minimize planar area and prevent electrical isolation, allowing for efficient channel region control and inversion layer formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography processes are used to form fine patterns, then manufacturing precision can be maintained, but device complexity and manufacturing cost increase significantly
Solution Approach 1:
The device structure is segmented into multiple vertical layers including substrate, first insulating layer, second insulating layer, third insulating layer, and active regions at different depths. This vertical segmentation allows fine pattern formation through controlled etching and deposition at different levels, avoiding the need for complex photolithography while achieving high precision through layered architecture
Solution Approach 2:
The invention transitions from planar pattern formation to three-dimensional vertical structure formation. By creating active regions, conductive lines, and insulating layers at different vertical levels, the device achieves fine pattern precision through depth-based differentiation rather than relying solely on photolithographic resolution in the lateral dimension
2Quantity of substance
If integration density is increased through planar scaling, then device capacity improves, but short-channel effects and manufacturing difficulties worsen
Solution Approach 1:
The invention achieves high integration density by utilizing the vertical dimension with multiple stacked insulating layers and active regions at different depths. This three-dimensional arrangement increases the quantity of functional elements without reducing lateral feature sizes, thereby maintaining manufacturing feasibility while avoiding short-channel effects through controlled vertical geometry
Solution Approach 2:
Different regions of the device are assigned specific functions at different vertical levels: the substrate provides mechanical support, first and second insulating layers provide electrical isolation, third insulating layer provides additional isolation, and active regions provide conduction paths. This localized functional assignment optimizes each region's performance while collectively achieving high integration density with reliable electrical characteristics
3Quantity of substance
If conductive lines are placed to minimize planar area, then integration density improves, but electrical isolation control becomes more difficult
Solution Approach 1:
Conductive lines are positioned at different vertical levels within the device structure, with some conductive lines located between insulating layers and others at different depths. This vertical separation allows conductive lines to be closely spaced in the lateral dimension while maintaining electrical isolation through the insulating layers in the vertical dimension, thereby achieving high integration density without compromising isolation precision
Solution Approach 2:
The device is divided into multiple electrically isolated segments by inserting insulating layers between conductive lines and active regions. This segmentation creates distinct electrical zones that can be independently controlled, allowing conductive lines to be densely packed while maintaining precise electrical isolation through the insulating barrier layers
4Quantity of substance
If three-dimensional structures are implemented to increase integration density, then device capacity improves, but manufacturing process complexity increases
Solution Approach 1:
The three-dimensional structure is constructed through sequential formation of discrete layers: substrate, first insulating layer, second insulating layer, third insulating layer, and active regions. Each layer is formed through standard semiconductor processing steps performed in sequence, which simplifies manufacturing compared to forming complex three-dimensional structures in a single process, while still achieving high integration density through vertical stacking
Solution Approach 2:
Insulating layers are formed preliminarily before forming conductive lines and active regions. This preliminary action establishes the vertical electrical isolation framework in advance, which simplifies subsequent steps by providing predefined isolation boundaries, thereby reducing overall manufacturing process complexity while enabling three-dimensional integration
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances integration density and stability of semiconductor devices by controlling electric potential and preventing floating body effects, thereby improving the dynamic refresh characteristics and reliability of the semiconductor device.
Implementation Method 1
Each of the active patterns may include upper impurity regions formed in upper regions of the active pillars and a common lower impurity region formed below the active patterns
Implementation Method 2
The pillar anti-isolation mechanism may be positioned to create an inversion layer in a portion of the common lower impurity region
Implementation Method 3
auxiliary conductive lines may be disposed in the first trenches to cover and cross the outer sidewalls of the pair of active pillars
Data Source
AI summary
A semiconductor device includes a semiconductor substrate including first trenches defining outer sidewalls of a pair of active pillars and a second trench defining opposing inner sidewalls of the pair of active pillars. The second trench may have a bottom surface located at a higher level than bottom surface of the first trench. Auxiliary conductive lines may be disposed in the first trenches to cover and cross the outer sidewalls of the pair of active pillars. A pair of main conductive lines may be disposed in a pair of recessed regions that are laterally recessed from lower portions of the inner sidewalls of the active pillars into the pair of active pillars. A common impurity region may be disposed in the semiconductor substrate under the second trench. Upper impurity regions may be disposed in upper portions of the active pillars.