Semiconductor Active Region via Spacer Patterning
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Solution Overview
Problem
The challenge in semiconductor memory devices is to reduce the size of the cell region while maintaining the critical dimension and minimizing storage node contact resistance, which is difficult due to limitations in lithography resolution and the need for high integration of patterns within a limited space.
Innovation Solution
A method of manufacturing a semiconductor device involves forming a first trench with a line-shape on a semiconductor substrate, creating a wall oxide on the surface, and filling it with an oxide layer to form an active region, followed by forming a second trench with a uniform gap and filling it with an oxide layer, using techniques such as CMP and spacer patterning to achieve reduced critical dimensions and improved contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the critical dimension is reduced to increase integration density, then the memory capacity increases, but the lithography resolution limit is exceeded making pattern formation difficult
Solution Approach 1:
The patent applies segmentation by dividing the pattern formation process into multiple stages. Instead of attempting to form all patterns in a single lithography step, the method segments the critical dimension formation into: (1) forming a mandrel pattern at a larger dimension that is within lithography capabilities, (2) depositing a spacer material around the mandrel, and (3) selectively removing the mandrel to leave only the spacer-defined patterns. This segmentation allows the final critical dimension to be determined by the spacer thickness rather than the lithography resolution limit.
Solution Approach 2:
The patent uses an intermediary approach by introducing a spacer material as a mediating element between the lithography process and the final pattern. The spacer acts as an intermediary that translates a larger, easily-formed mandrel pattern into a smaller, high-precision final pattern. The spacer thickness, controlled by atomic layer deposition (ALD), serves as the intermediary parameter that determines the critical dimension, bypassing the need for direct high-resolution lithography.
2Productivity
If the cell region size is reduced to increase memory capacity, then the integration density improves, but the storage node contact resistance increases
Solution Approach 1:
The patent applies local quality by differentiating the treatment of different regions. The spacer material is selectively formed only in specific locations where storage node contacts are needed, while other regions receive different treatments. This localized approach ensures that contact resistance is optimized in critical areas without compromising the overall cell region size reduction. The spacer defines precise contact regions, ensuring low resistance paths are formed only where required for storage node access.
3Productivity
If more patterns are formed in the cell region to increase memory size, then the capacity increases, but the manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-forming the spacer material around the mandrel structure before final pattern definition. This preliminary spacer formation establishes the critical dimensions early in the process, allowing subsequent steps to work with pre-defined boundaries. The spacer acts as a pre-established template that guides subsequent etching and deposition processes, reducing the complexity of forming multiple precise patterns later in the manufacturing sequence.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the securement of active region size, reduction of storage node contact resistance, and efficient reduction of critical dimensions in semiconductor devices, enabling higher integration density without the limitations of traditional lithography.
Implementation Method 1
performing CMP with the semiconductor substrate as an etch stop layer and removing an oxide layer of an upper portion of the first trench
Implementation Method 2
forming a wall oxide on a surface of the first trench
Data Source
AI summary
A semiconductor device includes a semiconductor substrate having a trench defining an active region. A wall oxide is formed on side walls of the active region extending in the longitudinal direction, and an element isolation layer is formed in the trenches. A method of manufacturing a semiconductor device includes forming line-shape first trenches on a semiconductor substrate so as to define an active region; forming a wall oxide on surfaces of the first trenches; forming a second trench which separates the active region into a plurality of active regions; and filling the trenches with an element isolation layer.