Semiconductor Adder Circuit Reducing Power via Shift Selection
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Solution Overview
Problem
Existing semiconductor devices with multiplier circuits face inefficiencies in power consumption due to glitches in adder circuits, particularly in Wallace tree structures, which are exacerbated by the need for multiple adders to handle various multiples of the multiplicand, leading to increased power consumption and chip size.
Innovation Solution
The semiconductor device incorporates a configuration with a first adder generating non-2n multiples of the multiplicand and a selection circuit within each multiplier circuit, reducing the number of adders needed by using shift circuits to generate 2n values, thereby minimizing power consumption and chip size by eliminating unnecessary adders in the Wallace tree circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple adders are arranged in a Wallace tree structure to handle various multiples of the multiplicand, then multiplication capability is improved, but power consumption increases due to glitch propagation
Solution Approach 1:
The patent extracts and removes unnecessary adders from the Wallace tree structure by identifying that certain multiples (specifically 2^n multiples) can be generated more efficiently through shift operations rather than addition. This extraction of redundant components directly reduces glitch propagation and power consumption while maintaining multiplication capability.
Solution Approach 2:
The patent changes the operational parameters of the multiplier circuit by introducing a mode selection mechanism that can switch between different multiplication methods (Wallace tree with adders versus shift-based multiplication). This parameter change allows optimization of power consumption based on the specific multiplication requirements.
2Productivity
If multiple adders are arranged in a Wallace tree structure to handle various multiples of the multiplicand, then multiplication capability is improved, but chip size increases
Solution Approach 1:
The patent extracts and removes unnecessary adders from the Wallace tree structure by identifying that certain multiples (specifically 2^n multiples) can be generated more efficiently through shift operations rather than addition. This extraction of redundant components directly reduces chip area while maintaining multiplication capability.
Solution Approach 2:
The patent merges the function of generating 2^n multiples from separate adder operations into a unified shift operation. This merging consolidates multiple discrete components into a single functional unit, reducing overall chip area while preserving the ability to handle various multiples of the multiplicand.
3Reliability
If adders are used to generate all multiples of the multiplicand, then multiplication accuracy is maintained, but the number of adders increases leading to more glitches
Solution Approach 1:
The patent extracts and removes unnecessary adders from the Wallace tree structure by identifying that certain multiples (specifically 2^n multiples) can be generated more efficiently through shift operations rather than addition. This extraction of redundant components directly reduces glitch propagation and power consumption while maintaining multiplication capability.
Solution Approach 2:
The patent introduces shift circuits as intermediary components between the multiplicand and the Wallace tree structure. These shift circuits serve as mediators that generate specific multiples (2^n) without requiring adders, thereby reducing the overall number of adders and glitch propagation while maintaining multiplication accuracy.
Data Source
AI summary
According to the embodiments, a semiconductor device includes: an adder configured to generate positive multiple data of the multiplicand which is used for a plurality of the multiplication in plurality and does not include a value of 2n (n is a positive integer) of the multiplicand; a Wallace tree circuit provided in each of the multiplier circuits and configured to operate a sum of a plurality of partial products by using a plurality of adders; and a selection circuit provided in each of the multiplier circuits and configured to select, according to a plurality of bits selected from the multiplier, data falling in a multiple of one of the multiplicand, data of 2n of the multiplicand, and the positive multiple data from the adder in order to output as one partial product of the plurality of partial products to the Wallace tree circuit.