Semiconductor Address Decoder Dynamic Masking for Yield Repair

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Solution Overview

Problem

Highly integrated semiconductor devices face issues with increased failed memory cells, leading to lower fabrication yields, and existing fuse-based repair methods are ineffective once devices are encapsulated, as general fuses cannot be programmed post-packaging.

Innovation Solution

A semiconductor system that controls the connection between address decoders and fuse circuits using masking signals generated in synchronization with clock pulses, allowing for selective enablement or disablement of connections to reduce the load on address decoders and improve yield by cutting off unused decoder connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the address decoder is connected to all fuse circuits, then all memory banks can be accessed, but the load on the address decoder increases and unused decoders consume unnecessary resources

Engineering Contradiction:
Improvememory bank selectionVSAvoidaddress decoder load
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic control of the address decoder connections through masking signals that are generated based on the bank address. The masking signals dynamically enable or disable specific address decoders depending on which memory bank is being accessed, transforming a static always-connected architecture into a dynamic selectively-connected one. This reduces the effective load on address decoders while maintaining full adaptability to access any memory bank.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent segments the address decoder functionality by dividing it into multiple independent decoders (first address decoder, second address decoder, etc.), each responsible for specific memory banks. The masking signals selectively activate only the relevant decoder segments based on the target bank, allowing the system to maintain versatility while reducing the operational complexity and resource consumption of each individual decoder.

Inventive Principle:
Principle #1Segmentation

2Ease of repair

If general fuses are used for repairing defective memory cells, then repair information can be stored, but the fuses cannot be programmed after device encapsulation

Engineering Contradiction:
Improvedefective memory cell repairVSAvoidpost-packaging programming
Core Design Contradiction:
Ease of repairVSEase of manufacture

Solution Approach 1:

The patent replaces the mechanical laser-based fuse programming method with an electrical programming mechanism. Instead of using laser beams to melt and open physical fuses during wafer fabrication, the system uses electrical signals applied to e-fuse structures (implemented as transistors) to change their resistance states. This electrical substitution enables programming to be performed after device encapsulation, as electrical connections can be maintained through the package while mechanical laser access cannot.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the fundamental parameter used for fuse programming from optical (laser beam energy) to electrical (voltage and current applied to transistor gates). By using electrical parameters to control the resistance state of e-fuse transistors rather than optical parameters to melt traditional fuses, the system enables post-packaging programming capability while maintaining the ability to store repair information for defective memory cells.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10629249B2Semiconductor device and semiconductor system
Publication Date: 2020.04.21 SK HYNIX INC
  • US10629249B2 patent drawing
  • US10629249B2 patent drawing
  • US10629249B2 patent drawing

AI summary

A semiconductor system includes a first semiconductor device and a first semiconductor device. The first semiconductor device outputs a clock, a chip selection signal and addresses. The second semiconductor device generates a masking signal from the addresses inputted in synchronization with a first pulse of the clock in response to the chip selection signal and decodes internal addresses generated from the addresses inputted in synchronization with a second pulse of the clock to select a word line. The second semiconductor device controls a connection between an address decoder and a fuse circuit in response to the masking signal. The address decoder selects the word line.