Semiconductor Address Input Circuit for Low-Temperature Row Operation
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Solution Overview
Problem
Current semiconductor devices face challenges in efficiently performing row operations in memory cell arrays due to delayed turn-on timing and voltage level issues, particularly in low-speed operations and varying temperature conditions.
Innovation Solution
The semiconductor device incorporates an address input circuit that boosts the voltage level of row addresses and a word line selection signal generation circuit to drive signals for selecting word lines, ensuring sufficient gate voltage and timing differences between row and column operations, even in low-speed states and low temperatures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voltage boosting is applied to row address bits, then turn-on timing is improved and operation reliability is enhanced, but device complexity increases due to additional boosting circuitry
Solution Approach 1:
The row address is segmented into multiple bits, with at least one bit (e.g., LSB) selectively boosted through dedicated boosting circuitry while other bits are processed normally. This segmentation allows targeted voltage enhancement only where needed, improving turn-on timing for critical address bits without unnecessarily complicating the entire address decoding circuitry.
Solution Approach 2:
Voltage boosting is applied locally to specific address bits that require enhanced drive strength, rather than uniformly boosting all address bits. The boosting circuitry is selectively configured to enhance only the necessary bits (e.g., least significant bits that control word line selection), maintaining overall circuit simplicity while addressing specific timing requirements.
2Loss of time
If voltage boosting circuitry is added to enhance row address signals, then timing performance is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The voltage boosting is performed preliminarily on the row address bits before they are decoded and used to select word lines. By pre-boosting the voltage of critical address bits early in the signal path, the circuit ensures adequate drive strength is available from the outset, eliminating timing delays that would otherwise require more complex compensating circuitry later in the manufacturing process.
3Productivity
If selective voltage boosting is applied to address bits, then operation efficiency is maintained in low-speed states, but circuit complexity increases
Solution Approach 1:
The voltage boosting circuitry is dynamically controlled based on operational requirements. The boosting is selectively activated for specific address bits depending on the operational state (e.g., low-speed vs. high-speed modes), allowing the circuit to adapt its complexity level to match the current performance requirements. This dynamic approach maintains operation efficiency across varying conditions without permanently increasing circuit complexity.
Data Source
AI summary
A semiconductor device includes an address input circuit configured to boost a voltage level of at least one bit of a row address to generate a boosting address and to drive a signal of a first node based on other bits of the row address and the boosting address. The semiconductor device also includes a word line selection signal generation circuit configured to drive a signal of a second node based on the signal of the first node and to generate a word line selection signal for selecting a word line based on the signal of the second node.