Semiconductor Address Interface Circuit With Supplementary Register
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Solution Overview
Problem
In multiprocessor systems, existing technologies face challenges in reducing the number of external terminals required for address input, limiting the efficiency and cost-effectiveness of accessing processor resources due to the limitations in the number of external terminals available.
Innovation Solution
A semiconductor device employing an external interface circuit with a supplementary register and mode register to generate address signals, allowing access to a wider address space with a reduced number of external terminals by supplementing address information and using multiplex terminals to input address and data in a switching manner.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the number of external terminals is reduced, then system cost is reduced and device complexity is reduced, but the address space that can be accessed is limited
Solution Approach 1:
The patent embeds a supplementary register within the external interface circuit that stores additional address bits. When an external access request arrives with a limited number of address terminals, the address control circuit combines these external address bits with the supplementary address bits from the nested register to form a complete address, effectively nesting the supplementary address storage within the interface circuit structure.
Solution Approach 2:
The address control circuit acts as an intermediary between the external terminals and the internal address space. It receives partial address information from external terminals, retrieves supplementary address bits from the supplementary register, combines them according to control signals, and generates the complete address for internal resource access, thereby mediating between limited external terminals and the full address space.
2Ease of manufacture
If the number of external terminals is reduced, then manufacturing cost is reduced, but the speed of address generation may be affected
Solution Approach 1:
The supplementary address bits are pre-loaded into the supplementary register before external access requests arrive. This preliminary action ensures that when an external access request is received, the address control circuit can immediately combine the external address bits with the pre-available supplementary bits without waiting for additional memory access, thereby maintaining high address generation speed while using fewer external terminals.
3Adaptability or versatility
If more external terminals are used, then a wider address space can be accessed, but the number of external connections increases
Solution Approach 1:
The patent segments the 32-bit address into two parts: external address bits that are transmitted through external terminals, and supplementary address bits that are stored internally in the supplementary register. This segmentation allows the system to access a full 32-bit address space while using fewer external terminals, as the supplementary bits are provided internally rather than requiring additional external connections.
Data Source
AI summary
There is provided a semiconductor device having a reduced number of external terminals allocated for address input to receive access from outside, while realizing a high-speed response to an access from outside.The semiconductor device employs, in order to allow other external devices to directly access resources it possesses in its own address space, in an external interface circuit, external terminals which input a part of the address signal required for access from outside, a supplementary register which supplements the upper portion of address information that has been input from the external terminals, a mode register accessible from outside, and an address control circuit which generates an address signal to access the address space in a form based on information input from the external terminals, required supplementary information, and mode information of the mode register.