Semiconductor Address Processing Circuit for Multi-Bank Column Operations
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Solution Overview
Problem
Current semiconductor devices face challenges in efficiently performing column operations across multiple bank groups without the need for additional circuitry for address inversion, leading to increased complexity and area requirements.
Innovation Solution
The semiconductor device incorporates a command generation circuit, pipe control circuit, and address processing circuit to generate and manage bank group and column addresses through internal inversion or non-inversion based on burst operations, eliminating the need for a separate address inversion circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a separate address inversion circuit is added to perform column operations across multiple bank groups, then the operational versatility is improved, but the device complexity and area requirements increase
Solution Approach 1:
The patent combines the address inversion function with the existing address processing circuit by integrating an inverter directly into the address processing path. This merging eliminates the need for a separate address inversion circuit, thereby maintaining column operation versatility across multiple bank groups while reducing overall device complexity and area requirements
Solution Approach 2:
The address processing circuit is designed to perform multiple functions: it can process addresses for single bank group operations, invert addresses for multi-bank group column operations, and generate both row and column addresses. This multi-functionality allows the same circuit to adapt to different operational modes without requiring dedicated separate circuits for each function
2Adaptability or versatility
If a separate address inversion circuit is added to support multi-bank group column operations, then the operational versatility is improved, but the device area increases
Solution Approach 1:
The inverter is merged into the existing address processing circuit architecture, sharing the same physical space and resources. This integration approach enables address inversion for multi-bank group operations without requiring additional dedicated circuit area, thus maintaining versatility while minimizing area increase
3Productivity
If additional circuitry for address inversion is implemented, then the column operation efficiency across bank groups is improved, but the device complexity increases
Solution Approach 1:
The address inversion is performed as part of the preliminary address processing stage, before the actual column operation begins. By integrating the inverter into the address processing circuit, the inversion happens automatically as part of the address generation process, improving column operation efficiency without adding complex control logic or separate processing stages
Data Source
AI summary
A semiconductor device includes: a command generation circuit configured to generate a write strobe signal; a pipe control circuit configured to generate first to fourth input control signals and first to fourth output control signals which are sequentially enabled, when first and second write command pulses are inputted, and generate first to fourth internal output control signals after a preset period; and an address processing circuit configured to latch an address inputted through a command address, when the write strobe signal and the first to fourth input control signals are inputted, generate a bank group address and a column address from the latched address, when the first to fourth output control signals are inputted, and generate the bank group address and the column address by inverting the latched address, when the first to fourth internal output control signals are inputted.