Semiconductor Package Adhesion Patterns for Crack Reduction
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Solution Overview
Problem
The challenge in semiconductor packaging is to minimize crack generation and reduce the crack generation area, particularly in image sensor chips, which require slimness, high density, low power consumption, and high reliability, while maintaining functionality and resolution.
Innovation Solution
The solution involves a semiconductor package design with first and second adhesion patterns on the chip's surface, where the second adhesion patterns protrude towards the pixel area and overlap external connection terminals, reinforcing the chip's strength and reducing crack formation by dispersing external forces effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external connection terminals are mounted on the semiconductor chip, then electrical connection functionality is achieved, but cracks are generated and reliability is reduced
Solution Approach 1:
The patent applies preliminary action by forming adhesion patterns on the chip surface before mounting external connection terminals. These adhesion patterns are pre-positioned to overlap with the terminal locations, creating a preparatory bonding structure that prevents crack generation during subsequent mounting and operation processes.
Solution Approach 2:
The adhesion patterns serve as an intermediary element between the semiconductor chip and the external connection terminals. This intermediate layer distributes mechanical stress and prevents direct stress concentration at the terminal-chip interface, thereby reducing crack generation while maintaining electrical connection functionality.
2Length of moving object
If the chip is made thinner to achieve slimness, then package thickness is reduced, but mechanical strength decreases and crack susceptibility increases
Solution Approach 1:
The patent employs composite material structure by combining the semiconductor chip with adhesion patterns formed on its surface. This composite structure enhances the mechanical strength of the thin chip through the additional adhesion layer, allowing the package to achieve slimness while maintaining sufficient mechanical strength and crack resistance.
Solution Approach 2:
The adhesion patterns are strategically positioned at specific locations on the chip surface, particularly where external connection terminals will be mounted. This local reinforcement provides enhanced mechanical strength precisely where needed, allowing the overall chip to remain thin while preventing cracks at critical stress points.
Data Source
AI summary
A semiconductor package and a method for manufacturing the same are provided. The semiconductor package includes a semiconductor chip having a first surface, a second surface and a pixel area, first adhesion patterns disposed on the first surface, second adhesion patterns disposed between the first adhesion patterns and the pixel area and disposed on the first surface, and external connection terminals disposed on the second surface, wherein the second adhesion patterns and the external connection terminals are disposed to overlap each other.