Semiconductor Device Adhesive Layer Delamination Prevention
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Solution Overview
Problem
The semiconductor industry faces challenges in further reducing the physical size of semiconductor devices while maintaining functionality, as traditional bonding processes are complex and inefficient, particularly in achieving high integration density and minimizing delamination risks in stacked semiconductor devices.
Innovation Solution
A method involving a carrier substrate with an adhesive layer, a polymer layer, and seed layers to form through vias and redistribute connections, allowing for the stacking and bonding of semiconductor devices with enhanced adhesion and reduced delamination risks, using techniques like electroplating and laser drilling for precise patterning and exposure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional bonding processes are used for stacked semiconductor devices, then device functionality is maintained, but manufacturing complexity increases and delamination risk increases
Solution Approach 1:
The patent applies preliminary action by forming an adhesive layer on the carrier substrate before bonding the semiconductor die. This adhesive layer is prepared in advance to ensure proper adhesion and prevent delamination during subsequent processing steps, thereby reducing delamination risk while maintaining manufacturing feasibility
Solution Approach 2:
The patent introduces an adhesive layer as an intermediary substance between the carrier substrate and the semiconductor die. This intermediary material facilitates reliable bonding and prevents delamination, resolving the contradiction between maintaining simple processes and achieving high reliability
2Quantity of substance
If minimum feature size is reduced to increase integration density, then more components can be integrated, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the bonding process into multiple controlled steps including carrier preparation, adhesive application, die bonding, and encapsulation. This segmentation allows each step to be optimized independently, enabling high integration density while maintaining manufacturing precision through controlled processing conditions
Solution Approach 2:
The patent employs parameter changes by controlling bonding temperature, pressure, and adhesive composition to achieve reliable bonding at reduced feature sizes. By adjusting these parameters, the process accommodates higher integration density while maintaining the manufacturing precision required for small features
3Volume of moving object
If stacked and bonded semiconductor devices are implemented to reduce physical size, then device footprint is reduced, but adhesion requirements increase
Solution Approach 1:
The adhesive layer is applied to the carrier substrate before die bonding, ensuring proper adhesion surfaces are prepared in advance. This preliminary action enables strong bonding interfaces that can support stacked device configurations while maintaining compact physical dimensions
Solution Approach 2:
The patent uses composite material structures including the adhesive layer composed of multiple materials (e.g., organic adhesive, inorganic adhesive, or adhesive tape) to achieve both strong adhesion and compact device size. The composite approach allows optimization of bonding strength while maintaining small form factor
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of smaller, more integrated semiconductor devices with improved adhesion and reduced delamination risks, enhancing manufacturing yield and efficiency by allowing for higher pin counts and more complex interconnects.
Implementation Method 1
a method includes bonding a semiconductor die to a carrier substrate using an adhesive layer
Implementation Method 2
The via is encapsulated in an encapsulant along with the semiconductor die
Implementation Method 3
patterning the polymer layer to expose a first lining layer of one of the plurality of vias
Data Source
AI summary
An integrated fan out package on package architecture is utilized along with de-wetting structures in order to reduce or eliminated delamination from through vias. In embodiments the de-wetting structures are titanium rings formed by applying a first seed layer and a second seed layer in order to help manufacture the vias. The first seed layer is then patterned into a ring structure which also exposes at least a portion of the first seed layer.