Insulating Adhesive Layer Placement for Semiconductor Dicing Yield
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Solution Overview
Problem
In semiconductor device manufacturing, the formation of insulating adhesive layers on both back and side faces to prevent short circuits can lead to positional shifts during the dicing process, resulting in errors and reduced dicing yield, especially when using conventional dicing methods like the dicer, which are not as precise as laser dicing.
Innovation Solution
A semiconductor device design where the insulating adhesive layer is specifically formed on the second major surface and two side faces of the semiconductor device body, extending to the dicing region, while maintaining the form of the element array until the final cutting stage, thereby minimizing positional shifts and reducing the risk of breakage during the dicing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the insulating adhesive layer is formed on both back and side faces of semiconductor devices, then short circuit prevention is improved, but positional shift during dicing increases causing breakage
Solution Approach 1:
The insulating adhesive layer is selectively formed only on the back face of the semiconductor device, not on the side faces. This localized application provides sufficient insulation to prevent short circuits between adjacent devices while minimizing the total adhesive volume that could cause positional shifts during dicing, thus resolving the contradiction between reliability and manufacturing precision
2Reliability
If the insulating adhesive layer is formed on side faces of semiconductor devices, then short circuit defects are reduced, but element breakage during dicing increases
Solution Approach 1:
The adhesive layer is applied locally only on the back face where it is most needed for device-to-substrate bonding and basic insulation, rather than covering the side faces. This selective placement maintains electrical isolation between devices while preserving the structural integrity of the elements during the dicing process by avoiding excessive adhesive on the sides
3Reliability
If insulating adhesive layer coverage is increased to ensure no short circuit, then electrical reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent extracts the adhesive application from the side faces, keeping it only on the back face. This simplification maintains the essential function of electrical insulation and mechanical bonding while reducing the overall process complexity by eliminating the need for precise side-face adhesive application and associated alignment controls
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the risk of positional shifts and breakage during dicing, enhancing the dicing yield and allowing for the miniaturization of semiconductor devices by ensuring precise alignment and coverage of only necessary areas with the insulating adhesive layer, thus improving manufacturing reliability and preventing unnecessary resource consumption.
Implementation Method 1
The insulating adhesive layer is provided to cover a second major surface of the semiconductor device body and one or two of four side faces of the semiconductor device body
Data Source
AI summary
According to one embodiment, a semiconductor device includes a semiconductor device body and an insulating adhesive layer. The semiconductor device body is formed with a square plate shape and has an element portion provided on a first major surface. The insulating adhesive layer is provided to cover a second major surface of the semiconductor device body and one or two of four side faces of the semiconductor device body.