Semiconductor Chip Adhesive Fillet and Sealing Contact
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Solution Overview
Problem
Semiconductor devices with BGA type configuration experience cracks at the connection portion between bonding wires and pad electrodes during temperature cycle tests, leading to open failures and reduced reliability due to thermal expansion mismatches between the semiconductor chip, adhesive layer, and sealing body.
Innovation Solution
The semiconductor device incorporates a semiconductor chip with a specific arrangement of pad electrodes and protection films, where the adhesive layer covers the back surface and side surfaces of the chip, forming a triangle fillet to reduce voids and stress, and uses a sealing body that contacts the organic protection film in the circuit formation region but not in the scribe region, thereby minimizing crack formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the adhesive layer covers the side surface of the semiconductor chip, then the adhesion between chip and wiring board is improved, but cracks occur at the connection portion between bonding wires and pad electrodes due to stress concentration
Solution Approach 1:
The patent applies different properties to different regions of the semiconductor chip side surface. The first region (near pad electrodes) has adhesive layer with controlled coverage to prevent stress concentration at bonding connections, while the second region (other side surface areas) maintains adhesive coverage for structural support. This localized differentiation resolves the contradiction by optimizing adhesion strength without compromising connection reliability.
2Reliability
If the sealing body contacts the protection film extensively, then the sealing performance is improved, but stress is transmitted to the bonding wire connection portions causing cracks
Solution Approach 1:
The patent creates different contact relationships between the sealing body and protection film in different regions. In the first region corresponding to pad electrode locations, the sealing body contacts the protection film to provide sealing while the adhesive layer configuration prevents stress transmission to bonding connections. In the second region, the sealing body has reduced or no contact with the protection film, minimizing stress transmission. This spatially differentiated approach maintains sealing performance while protecting connection strength.
3Stability of the object's composition
If the adhesive layer covers the entire back surface, then the mounting stability is improved, but thermal expansion stress concentrates at the bonding wire connection portions
Solution Approach 1:
The patent differentiates the adhesive layer coverage between regions. The first region (under pad electrodes) has controlled adhesive coverage that provides sufficient mounting stability while preventing stress concentration at bonding wire connections. The second region (other back surface areas) maintains full adhesive coverage for overall mounting stability. This localized differentiation resolves the contradiction between mounting stability and temperature cycle reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the reliability of the semiconductor device by reducing stress-induced cracks and improving adhesion between the sealing body and the chip, ensuring consistent performance across temperature cycles.
Implementation Method 1
The adhesive layer covers the entirety of the back surface of the semiconductor chip and at the same time, covers the second side surface of the semiconductor chip
Implementation Method 2
cracks occur at a connection portion between the bonding wires and the pad electrodes in a temperature cycle test performed, for example, with 2000 cycles of temperature raising and lowering within a range (from −65° C. to 15° C.)
Data Source
AI summary
To provide a semiconductor device having improved reliability. The semiconductor device has a wiring board, bonding land, semiconductor chip mounted on the wiring board via an adhesive layer and having a pad electrode, bonding wire connecting the pad electrode with the bonding land, and sealing body. The sealing body is, in a circuit formation region, in contact with an organic protection film and, in a scribe region and a region between the pad electrode and the scribe region, in contact with a surface protection film while not in contact with the organic protection film. A first side surface is closer to the circuit formation region side than a second one. The adhesive layer covers entirety of the semiconductor chip back surface and the second side surface of the semiconductor chip. The first side surface is in contact with the sealing body without being covered with the adhesive layer.