3D Semiconductor Stacking via Adhesive Layers and Metal Bumps
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Solution Overview
Problem
The semiconductor industry faces challenges in increasing circuit density beyond two-dimensional limits, with three-dimensional ICs requiring complex designs and incurring high costs due to low yield and costly bonding processes.
Innovation Solution
A semiconductor device and manufacturing method involving multiple semiconductor dies embedded in photosensitive layers with through vias and adhesive layers, connected using metal bumps, allowing for hybrid stacking with reduced yield penalties and minimized costs through a combination of bumpless and micro-bump stacking processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional ICs are formed by bonding multiple dies or chips together, then circuit density is increased, but manufacturing cost increases and yield decreases due to complex bonding processes
Solution Approach 1:
The patent applies preliminary action by forming through-vias and embedding adhesive materials in the photosensitive layers before the bonding process. The adhesive layers are prepared in advance on each wafer, eliminating the need for complex post-bonding alignment and reducing manufacturing complexity. This preliminary preparation enables simpler bonding operations while maintaining high circuit density through 3D stacking.
2Quantity of substance
If more semiconductor dies are integrated in one chip, then circuit density increases, but design complexity increases
Solution Approach 1:
The patent segments the integrated circuit into multiple separate wafers that are processed independently and then bonded together. Each wafer can be designed and optimized separately, reducing the complexity of designing a single large-scale integrated circuit. The segmentation approach allows parallel development of different functional blocks while achieving high overall circuit density through 3D integration.
Solution Approach 2:
The patent transitions from two-dimensional planar integration to three-dimensional vertical integration by stacking multiple wafers. This dimensional change allows circuit density to increase vertically rather than requiring ever-larger planar areas, thereby reducing design complexity while maintaining or increasing overall circuit capacity.
3Shape
If traditional bonding processes are used to connect multiple dies, then three-dimensional IC structure is achieved, but manufacturing yield decreases
Solution Approach 1:
The patent introduces adhesive layers as intermediary materials between the semiconductor dies to facilitate bonding. These adhesive layers, embedded in the photosensitive layers before bonding, act as mediators that simplify the bonding process and improve alignment accuracy. The intermediary adhesive materials reduce the sensitivity of the bonding process to misalignment and defects, thereby improving manufacturing yield while achieving the desired 3D structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-density three-dimensional ICs with improved yield rates and reduced costs by combining bumpless and micro-bump stacking, overcoming the limitations of two-dimensional integration and traditional 3D IC formation methods.
Implementation Method 1
a plurality of first semiconductor dies are embedded in a first photosensitive layer of a first group of wafers
Implementation Method 2
The first adhesive layer is disposed between at least two of the first group of wafers to form a first structure
Data Source
AI summary
A method for manufacturing a semiconductor device includes preparing a first group of wafers having a plurality of first semiconductor dies embedded in a first photosensitive material layer; forming a plurality of first through vias in the first photosensitive material layer; attaching at least two of the first group of wafers using a first adhesive layer to form a first structure; preparing a second group of wafers having a plurality of second semiconductor dies embedded in a second photosensitive material layer; forming a plurality of second through vias in the second photosensitive material layer; attaching at least two of the second group of wafers using a second adhesive layer to form a second structure; and connecting the first structure to the second structure with a plurality of first metal bumps.