Semiconductor Package Adhesive Film Extension Control

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Solution Overview

Problem

The existing semiconductor packages face reliability issues due to protruding extension portions of adhesive films during thermal compression bonding, which can cause defects and decrease the package's reliability.

Innovation Solution

A recess surface is introduced on the uppermost semiconductor chip to accommodate the uppermost adhesive film, controlling the height of its extension portion and reducing interference with lower adhesive films, thereby preventing exposure outside the encapsulant and enhancing package reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If adhesive films are used to bond semiconductor chips during thermal compression bonding, then the chips are securely attached, but the extension portions of the adhesive films protrude and cause defects

Engineering Contradiction:
Improvebonding strengthVSAvoidpackage reliability
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

The harmful extension portions of the adhesive films are extracted and removed through planarization processing, eliminating the defect source while preserving the bonding function of the adhesive films that remain within the encapsulant

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The encapsulant is designed to extend beyond the semiconductor chips, creating a preliminary containment structure that prevents adhesive film extension portions from protruding outward, thereby preventing defects before they occur

Inventive Principle:
Principle #9Preliminary anti-action

2Reliability

If adhesive films extend beyond the chip edges to ensure bonding coverage, then bonding reliability is improved, but the extension portions are exposed outside the encapsulant causing defects

Engineering Contradiction:
Improvebonding reliabilityVSAvoiddefects from exposed adhesive
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The encapsulant structure is designed in advance to extend beyond the chip edges, creating a containment barrier that prevents adhesive extension portions from being exposed, thereby eliminating defects before they can occur

Inventive Principle:
Principle #9Preliminary anti-action

Solution Approach 2:

Planarization processing is applied to remove the exposed extension portions of the adhesive films that protrude beyond the encapsulant, extracting the harmful elements while preserving the functional bonding portions

Inventive Principle:
Principle #2Taking out (Extraction)

3Area of stationary object

If multiple adhesive films are stacked in vertical layers, then bonding coverage is improved, but the uppermost adhesive film extension interferes with lower adhesive films

Engineering Contradiction:
Improvebonding coverage areaVSAvoidadhesive film layer stability
Core Design Contradiction:
Area of stationary objectVSStability of the object's composition

Solution Approach 1:

The interfering extension portions of the uppermost adhesive film are selectively removed through planarization, eliminating the interference with lower adhesive films while preserving the bonding coverage provided by all adhesive layers

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The problem of vertical interference between stacked adhesive films is resolved by transitioning to horizontal containment through the encapsulant structure, which covers the adhesive extensions in the horizontal plane, allowing multiple vertical layers to coexist without interference

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20240170440A1Semiconductor package
Publication Date: 2024.05.23 SAMSUNG ELECTRONICS CO LTD
  • US20240170440A1 patent drawing
  • US20240170440A1 patent drawing
  • US20240170440A1 patent drawing

AI summary

A semiconductor package includes first semiconductor chips electrically connected to each other through a through-via electrically connecting a first front surface pad and a first rear surface pad. A second semiconductor chip has a second lower surface including a second front surface pad, a second upper surface, a second side surface extending from the second upper surface, and a recess surface extending from the second lower surface to the second side surface. First adhesive films are on a first lower surface of first semiconductor chips and include first extension portions extending further outwardly than a first side surface of the first semiconductor chips. A second adhesive film is on the second lower surface and includes a second extension portion extending further outwardly than the second side surface. In a horizontal direction, a length of the second extension portion is less than a length of each of the first extension portions.