Semiconductor Aging Monitor Using Test and Reference Circuits
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Solution Overview
Problem
Modern semiconductor circuits face degradation issues such as NBTI, HCI, and PBTI due to shrinking transistor sizes and reduced voltage, leading to potential malfunction and performance degradation over time, especially under high temperatures and high switching events.
Innovation Solution
A circuit arrangement that includes a test circuit and a reference circuit, where the test circuit operates under stress conditions similar to functional circuits to simulate aging, while the reference circuit remains non-aged, allowing for direct comparison of performance to determine the aging state of semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the physical size of FETs is reduced to increase integration density, then the integration density is improved, but the susceptibility to degradation effects increases
Solution Approach 1:
The patent divides the monitoring function into separate test circuits and reference circuits. The test circuits are segmented and distributed throughout the semiconductor device to monitor different regions independently, allowing degradation to be detected at multiple locations without affecting the entire device's operation.
Solution Approach 2:
The patent introduces reference circuits as intermediary elements that provide a stable baseline for comparison. These reference circuits are designed to be less susceptible to degradation and serve as mediators against which the degradation of test circuits can be measured, enabling indirect monitoring of aging effects.
2Use of energy by moving object
If the voltage supply is reduced to save power, then the power consumption is reduced, but the degradation effects are accelerated
Solution Approach 1:
The patent implements preliminary monitoring through test circuits that continuously or periodically assess the state of functional circuits before degradation leads to malfunction. By detecting early signs of degradation, the system can take preventive actions such as adjusting operating parameters or alerting users to reduce further stress on the circuits.
Solution Approach 2:
The patent establishes feedback loops where the output of test circuits and reference circuits is compared to detect degradation. This feedback mechanism provides continuous information about the aging state of the semiconductor device, enabling dynamic adjustment of operating conditions to mitigate further degradation while maintaining acceptable performance.
3Measurement precision
If the test circuit operates synchronously with the clock to monitor aging under real conditions, then the accuracy of aging monitoring is improved, but the reference circuit may also degrade
Solution Approach 1:
The patent applies different quality characteristics to different parts of the monitoring system. Test circuits are designed to operate under full stress conditions synchronized with the clock to accurately reflect functional circuit aging. Reference circuits are designed with different characteristics - operating asynchronously or with reduced stress - to maintain stability and serve as a reliable baseline for comparison.
Solution Approach 2:
The patent introduces asymmetry in the operation of test and reference circuits. Test circuits operate synchronously with the clock signal to experience the same timing and switching conditions as functional circuits. Reference circuits operate asynchronously or with different clocking schemes, creating an asymmetric arrangement that allows differentiation between actual degradation and operational variations.
4Productivity
If switching events are increased to test circuit performance, then the productivity of testing is improved, but HCI degradation is accelerated
Solution Approach 1:
The patent uses partial action by implementing periodic or intermittent testing rather than continuous operation at maximum stress. Test circuits can be activated at different frequencies or duty cycles, allowing degradation monitoring without subjecting the circuits to excessive switching events that would accelerate HCI effects beyond acceptable levels.
Data Source
AI summary
Implementations are presented herein that include a test circuit and a reference circuit.