Semiconductor Device Air Gap Buffer for 3D Memory Stress
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Solution Overview
Problem
Three-dimensional nonvolatile memory devices face structural stress issues due to increased height, leading to performance degradation as the stack structure grows, making it challenging to maintain stability and integration.
Innovation Solution
Incorporating flexible buffers, such as air gaps, within the interlayer insulating layer between the cell and peripheral regions to absorb and buffer compressive and tensile stresses, thereby reducing the impact on the cell stack structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the height of the stack structure is increased to improve the degree of integration, then the integration density is improved, but the stress applied to the stack structure increases causing geometry changes and performance degradation
Solution Approach 1:
The patent introduces a buffer layer as an intermediary element between the stack structure and the interlayer insulating layer. This buffer layer absorbs and mitigates the stress transmitted from the interlayer insulating layer to the stack structure, allowing the stack height to be increased for higher integration while maintaining structural stability through the mediating buffer zone.
Solution Approach 2:
The patent modifies the physical and mechanical parameters of the buffer layer (such as its thickness, material composition, and elastic properties) to optimize its stress-absorbing capability. By adjusting these parameters, the buffer layer can effectively accommodate the stress generated by tall stack structures without causing geometric deformation, thus enabling high integration while preserving stack stability.
2Quantity of substance
If the height of the stack structure is increased to improve integration, then the storage capacity is improved, but the stress-induced geometry change increases leading to performance degradation
Solution Approach 1:
The buffer layer serves as a stress-absorbing intermediary that prevents stress-induced geometry changes in the stack structure. By placing this compliant layer between the rigid interlayer insulating layer and the precise stack structure, the patent protects the geometric precision of the stack while allowing for increased height and storage capacity.
Solution Approach 2:
The buffer layer is positioned beforehand to cushion and absorb stress before it can reach the stack structure. This preemptive stress absorption prevents geometry changes in the stack structure, maintaining manufacturing precision even as stack height and storage capacity are increased.
3Strength
If a rigid interlayer insulating layer is used to provide structural support, then the mechanical strength is improved, but the stress applied to the stack structure increases causing instability
Solution Approach 1:
The patent applies the principle of local quality by using different material properties in different regions: the interlayer insulating layer uses rigid materials for overall structural support and strength, while the buffer layer uses softer, more compliant materials locally at the interface with the stack structure to absorb stress and protect against instability. This spatial differentiation of material properties resolves the contradiction between strength and stability.
Solution Approach 2:
The patent employs composite material structures where the interlayer insulating layer and buffer layer are combined. The interlayer insulating layer provides macroscopic structural strength, while the buffer layer provides microscopic stress absorption. This composite approach allows the system to simultaneously achieve both mechanical strength and stack structure stability.
Data Source
AI summary
A semiconductor device includes a substrate including a cell region and a peripheral region adjacent to the cell region, a cell stack structure located in the cell region, the cell stack structure including vertical memory strings, a circuit located in the peripheral region, the circuit driving the vertical memory strings, and an interlayer insulating layer formed on the substrate to cover the cell stack structure and the circuit, and including air gaps located between the cell region and the peripheral region.