Semiconductor Interconnect Air Gap Formation via Capping Pattern Protection
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Solution Overview
Problem
In semiconductor manufacturing, existing methods face challenges in preventing copper diffusion into dielectric layers and ensuring efficient etching processes that protect interconnect layers from damage, leading to potential loss of copper and electrical isolation issues.
Innovation Solution
The method involves forming grooves in a dielectric layer, depositing a barrier layer and interconnect layer, recessing, and creating capping patterns to protect the interconnect layer during etching, followed by forming air gaps between grooves using selective etching processes to prevent copper diffusion and maintain electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper interconnect layers are formed in dielectric layers, then electrical connectivity is achieved, but copper diffusion into the dielectric layer occurs causing reliability issues
Solution Approach 1:
A barrier layer is introduced as an intermediary between the copper interconnect layer and the dielectric layer. This barrier layer prevents copper atoms from diffusing into the dielectric material, thereby maintaining electrical isolation and preventing reliability issues while allowing the copper interconnect to function properly.
Solution Approach 2:
The dielectric layer is segmented by forming air gaps between adjacent interconnect structures. These air gaps physically separate regions of the dielectric layer, preventing copper diffusion pathways and enhancing electrical isolation between adjacent interconnect lines.
2Reliability
If air gap structures are formed to prevent copper diffusion, then electrical isolation is improved, but manufacturing complexity increases
Solution Approach 1:
The air gap structure is formed preliminarily during the interconnect fabrication process by selectively removing portions of the dielectric layer before final copper deposition. This preliminary formation of air gaps simplifies subsequent processing steps and integrates the isolation structure into the main fabrication flow rather than adding separate complex steps.
3Reliability
If etching processes are used to form air gaps, then copper diffusion is prevented, but interconnect layer damage may occur
Solution Approach 1:
A capping pattern is used as a protective intermediary layer during the etching process. This capping pattern is deposited over the interconnect layer before etching the dielectric to form air gaps. The capping pattern protects the underlying interconnect layer from direct exposure to harsh etching conditions, preventing damage while allowing the dielectric etching to proceed.
Solution Approach 2:
The capping pattern is applied beforehand to cushion and protect the interconnect layer from the harmful effects of the etching process. This protective layer absorbs the mechanical and chemical stress of etching, preventing direct damage to the copper interconnect while still allowing the formation of air gaps in the dielectric layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents copper loss and ensures efficient electrical isolation by forming air gaps, enhancing the semiconductor device's performance and reliability.
Implementation Method 1
etching at least a portion of the first part by a first etching process, etching the at least a portion of the first part etched by the first etching process and the capping pattern, by a second etching process to form a trench
Implementation Method 2
forming a first barrier layer in each groove, conformally forming a second barrier layer on a sidewall and a bottom surface of the trench and on a top surface of the recessed interconnection layer
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming grooves in a first dielectric layer on a substrate, the first dielectric layer including a first part between the grooves, forming a first barrier layer and an interconnect layer in each groove, recessing the interconnect layer and the first barrier layer, forming a capping pattern on the recessed interconnect layer, etching at least a portion of the first part by a first etching process, sequentially etching the capping pattern and the at least a portion of the IMD part by a second etching process to form a trench, conformally forming a second barrier layer in the trench and on the recessed interconnection layer, and forming a second dielectric layer on the second barrier layer not to fill the trench such that an air gap is formed in the trench.