Semiconductor Damascene Process Air Gap Formation
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Solution Overview
Problem
The damascene process in semiconductor fabrication faces issues with non-uniform etch selectivity and metal gap fill limitations due to composite isolation layers, leading to irregular trench profiles and damage to low-k dielectric layers, which affect the R×C delay performance and capacitance of semiconductor devices.
Innovation Solution
A semiconductor fabricating process involving a first dielectric layer, a transitional layer, and a conductive fill, where the transitional layer is removed, and a second dielectric layer is formed over the conductive fill and first dielectric layer, with a second barrier layer conformally encompassing the protruded conductive fill to reduce dielectric constant and improve capacitance, using a non-conformal deposition scheme to create air gaps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a damascene process with composite isolation layers is used to form conductive interconnections, then the metal gap fill capability is improved, but the trench profile becomes irregular with upwardly narrowing tapered shape causing necking effect
Solution Approach 1:
The patent segments the isolation structure into multiple functional layers: a first isolation layer with first etch selectivity and a second isolation layer with second etch selectivity. This segmentation allows each layer to be optimized independently, where the first isolation layer provides mechanical support and the second isolation layer enables uniform trench etching, thereby resolving the contradiction between ease of manufacture and manufacturing precision.
Solution Approach 2:
The patent applies local quality by assigning different etch selectivities to different spatial regions through the use of composite isolation layers. The first isolation layer has a first etch selectivity ratio while the second isolation layer has a second etch selectivity ratio, allowing the etching process to proceed uniformly through the trench while maintaining overall structural integrity and enabling precise trench profile control.
2Productivity
If dry etch plasma is used to etch trenches in ELK material, then the conductive interconnections are formed, but the ELK layer is damaged forming a thin damaged layer with higher dielectric constant
Solution Approach 1:
The patent introduces an intermediary protective layer between the dry etch plasma and the ELK material. This protective layer acts as a buffer that allows the etching process to proceed while preventing direct plasma damage to the ELK layer, thus maintaining the low dielectric constant of the ELK material while still enabling conductive interconnection formation.
Solution Approach 2:
The patent applies preliminary anti-action by pre-forming a protective structure on the ELK layer before the dry etch plasma exposure. This protective structure is designed to counteract the harmful effects of plasma exposure, preventing the formation of damaged layers with higher dielectric constants while allowing the necessary etching to create conductive interconnections.
3Reliability
If the dielectric constant of inter-metal dielectric layer is reduced to improve R×C delay characteristic, then the capacitance decreases, but the manufacturing complexity increases due to material selection constraints
Solution Approach 1:
The patent employs composite materials by combining multiple dielectric layers with different properties. The first isolation layer and second isolation layer are made from different materials or have different densities, creating a composite structure that achieves the desired low effective dielectric constant while maintaining manufacturability. This composite approach allows optimization of R×C delay characteristics without excessive manufacturing complexity.
Solution Approach 2:
The patent utilizes parameter changes by adjusting the density and composition of the isolation layers. By controlling the density ratio between the first and second isolation layers, and adjusting their respective dielectric constants, the patent optimizes the overall R×C delay characteristic while maintaining practical manufacturing constraints and material availability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents damage to the low-k dielectric layer, reduces the dielectric constant, and enhances the R×C delay performance by forming air gaps, thereby improving the overall capacitance and resistance characteristics of the semiconductor device.
Implementation Method 1
using a non-conformal deposition scheme to create air gaps
Data Source
AI summary
A semiconductor structure and a fabricating process for the same are provided. The semiconductor fabricating process includes providing a first dielectric layer, a transitional layer formed on the first dielectric layer, and a conductive fill penetrated through the transitional layer and into the first dielectric layer; removing the transitional layer; and forming a second dielectric layer over the conductive fill and the first dielectric layer.