Semiconductor Wiring with Air Gaps to Reduce Parasitic Capacitance
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Solution Overview
Problem
As semiconductor devices integrate more densely, the parasitic capacitance between neighboring wiring patterns increases, leading to RC delay and reduced operational speed.
Innovation Solution
The semiconductor device incorporates a diffusion prevention insulation pattern with protrusions, conductive patterns having inclined sidewalls, a barrier layer, and an insulating interlayer with air gaps between conductive patterns, reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the integration degree of semiconductor device is increased, then the wiring density is improved, but the parasitic capacitance between neighboring wiring patterns increases causing RC delay and reduced operational speed
Solution Approach 1:
The patent introduces air gaps (porous structures) between neighboring conductive patterns in the wiring layer. These air gaps have significantly lower dielectric constants compared to conventional insulating materials, thereby reducing the parasitic capacitance between adjacent wires. This allows higher wiring density to be achieved without proportionally increasing RC delay, preserving operational speed despite increased integration.
2Productivity
If the line width and pitch of wiring patterns are decreased, then the wiring density is improved, but the parasitic capacitance between neighboring wiring patterns increases
Solution Approach 1:
By incorporating air gaps with low dielectric constants between closely spaced conductive patterns, the patent effectively reduces parasitic capacitance even when line widths and pitches are reduced to increase wiring density. The air gaps act as electrical insulators with minimal capacitive coupling effect.
Solution Approach 2:
The patent uses a composite structure combining conductive patterns (metal wires) with air gap insulators. This composite wiring structure achieves both high density (through small pitch) and low parasitic capacitance (through air gap insulation), resolving the contradiction between density and capacitance.
Data Source
AI summary
Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.