Semiconductor Air-Gap Structure for Lower DRAM Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The high process cost and poor effectiveness of forming air gaps to reduce bit line parasitic capacitance in DRAM processes are challenges in semiconductor technology.
Innovation Solution
A fabrication method involving the formation of a dielectric layer that covers the gap openings but does not fill them, allowing for easy removal of a sacrificial spacer layer to create air gaps, thereby simplifying the process and reducing costs while effectively forming air gaps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If air gap is formed to reduce parasitic capacitance, then parasitic capacitance reduction is improved, but process cost increases and formation effect deteriorates
Solution Approach 1:
The method forms a dielectric layer in advance that covers the gap openings between landing pad structures but does not fill the gaps themselves. This preliminary action enables subsequent easy removal of sacrificial spacer layers to create air gaps, thereby reducing parasitic capacitance between bit lines and node contacts while avoiding the high costs and poor effects of conventional air gap formation methods
Solution Approach 2:
The dielectric layer serves as an intermediary element that covers gap openings while leaving the gaps themselves open. This intermediary structure allows the sacrificial spacer layer to be easily removed and enables air gap formation without requiring complex direct air gap creation processes, thus reducing both process cost and improving formation effectiveness
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method achieves air gaps with a good effect, reducing parasitic capacitance efficiently and cost-effectively by avoiding residue issues and simplifying the fabrication process.
Implementation Method 1
a dielectric layer is formed on the landing pad structures and the first conductive layers, where the dielectric layer covers an opening of the gap
Implementation Method 2
The sacrificial spacer layer is removed by adopting the wet etching process to form the air gaps
Implementation Method 3
The first insulating layer covering the top surface of the sacrificial spacer layer and the top surface of each of the landing pad structures is removed by adopting a dry etching process, to expose the top surface of the sacrificial spacer layer
Implementation Method 4
the entire first insulating layer located in the array region is removed by adopting a wet etching process, to expose the top surface of the sacrificial spacer layer
Data Source
Figure 1
Figure 2a~2b
Figure 2c~2d
AI summary
A fabrication method for a semiconductor structure and a semiconductor structure are provided. The fabrication method for a semiconductor structure includes the steps as follows. A substrate is provided; multiple landing pad structures arranged at intervals are formed on an array region of the substrate, first conductive layers are formed on a peripheral region of the substrate, and a sacrificial spacer layer is formed on at least one side of each of the landing pad structures, where a gap exists between two adjacent ones of the landing pad structures; a dielectric layer is formed on the landing pad structures and the first conductive layers, where the dielectric layer covers an opening of the gap; the dielectric layer in the array region is removed and the gap is exposed; and the sacrificial spacer layer is removed to form air gaps.