Semiconductor Air-Gap Fabrication via 2D Material Layer
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Solution Overview
Problem
The increasing demand for semiconductor devices with enhanced functionality and miniaturization leads to RC delay issues due to parasitic capacitance, hindering electrical signal transmission speeds.
Innovation Solution
A method of fabricating semiconductor devices that includes forming a two-dimensional material layer to define an air-gap, where the layer covers the upper surface of a structure with an opening, growing in both transverse and longitudinal directions to maximize the air-gap volume without covering the sidewalls, thereby minimizing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the degree of integration and miniaturization of semiconductor elements is increased, then functionality and performance requirements are met, but RC delay increases and electrical signal transmission speeds decrease
Solution Approach 1:
The patent extracts the harmful dielectric material filling the gaps between semiconductor elements and replaces it with air gaps. By removing the material that causes parasitic capacitance and RC delay, the electrical signal transmission speed is improved while maintaining the high degree of integration.
Solution Approach 2:
The patent introduces air gaps (porous structure) between semiconductor elements to reduce parasitic capacitance. The air-gap structure acts as a low-dielectric constant region that minimizes electromagnetic interference and improves signal transmission speed without compromising device integration.
2Speed
If two-dimensional material layer is formed to define air-gap, then parasitic capacitance is reduced and RC delay improves, but manufacturing process complexity increases
Solution Approach 1:
The patent changes the physical and chemical parameters of the material layer (using two-dimensional materials with specific thickness and dielectric properties) to achieve air-gap formation. By controlling the thickness and material properties, the parasitic capacitance is reduced while the process remains manageable through precise parameter control.
Solution Approach 2:
The patent uses composite structures combining two-dimensional material layers with air gaps to create a non-conductive material layer. This composite approach leverages the unique properties of two-dimensional materials (such as graphene or hBN) to achieve both electrical isolation and mechanical stability, reducing parasitic capacitance while maintaining process feasibility.
Data Source
AI summary
A method of fabricating a semiconductor device including a two-dimensional material layer defining an air-gap, and the semiconductor device therefrom are provided. The method of fabricating a semiconductor device, includes forming a structure on a substrate, wherein the structure has an opening; loading the substrate into a process chamber; forming at least one two-dimensional material layer on an upper surface of the structure so as to overlie the opening and form an air-gap, wherein an upper portion of the air-gap is defined by the at least one two-dimensional material layer; and unloading the substrate from the process chamber.