Semiconductor Filling Layer With Air Gaps for Lower Parasitic Capacitance
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Solution Overview
Problem
As semiconductor devices are scaled down, issues such as parasitic capacitance increase, leading to reduced performance, reliability, and yield, while also increasing complexity.
Innovation Solution
The introduction of a filling layer made of boron carbonitride with a low dielectric constant and the incorporation of air gaps within this layer help reduce parasitic capacitance between conductive structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are scaled down to improve computing ability, then device density and integration are improved, but parasitic capacitance increases and performance deteriorates
Solution Approach 1:
The patent introduces a filling layer with porous structure containing air gaps (voids) within the dielectric material. These air gaps have extremely low dielectric constant (接近1), which significantly reduces parasitic capacitance between conductive structures while maintaining the scaled-down device dimensions and high density integration.
Solution Approach 2:
The filling layer is formed as a composite structure combining dielectric material with air gaps (voids). This composite approach creates a material with effective dielectric constant lower than the base dielectric material alone, achieving reduced parasitic capacitance while maintaining mechanical integrity and electrical insulation properties.
2Ease of manufacture
If conventional dielectric materials are used in scaled devices, then manufacturing is simplified, but parasitic capacitance increases reducing performance
Solution Approach 1:
The air gaps are formed preliminarily during the dielectric layer deposition process itself, rather than requiring separate post-processing steps. The deposition conditions are controlled to naturally create voids within the filling layer, integrating the low-k structure formation into the standard manufacturing flow.
Solution Approach 2:
The dielectric constant parameter of the filling layer is reduced by incorporating air gaps, changing the electrical properties of the material. This parameter change directly addresses the parasitic capacitance issue while the deposition process parameters are adjusted to achieve the desired porous structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively improves the performance of semiconductor devices by reducing parasitic capacitance, thereby enhancing reliability and yield while simplifying the device design.
Implementation Method 1
a filling layer made of boron carbonitride with a low dielectric constant
Data Source
AI summary
The present disclosure provides a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate; a gate electrode disposed on the substrate; a source region and a drain region disposed in the substrate and on opposite sides of the gate electrode; an isolating layer disposed over the substrate and the gate electrode; a plurality of metal contacts disposed in the gate electrode, the source region, and the drain region; a plurality of conductive plugs disposed in the isolating layer and electrically coupled to the metal contacts; a contact liner surrounding the conductive plugs; and a filling layer disposed in the isolating layer. The filling layer includes boron carbonitride.