Semiconductor Floating Gate Air Gap Parasitic Capacitance
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Solution Overview
Problem
Current semiconductor manufacturing methods fail to effectively prevent parasitic capacitance and tunnel coupling between adjacent floating gates in semiconductor devices, leading to reduced operational reliability and performance due to insufficient spacing and material interactions.
Innovation Solution
A method involving the formation of air gaps between gate patterns by selectively removing portions of the tunnel insulating layer and substrate, using materials like tetra ethyl ortho silicate (TEOS) and plasma enhanced-TEOS for the insulating layers, and employing capping layers to create a structure where the air gap's bottom is lower than the floating gate's surface, thereby reducing parasitic capacitance and tunnel coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional manufacturing methods are used without air gaps, then device structure is simpler, but parasitic capacitance and tunnel coupling between adjacent floating gates increase
Solution Approach 1:
The patent divides the continuous insulating layer into segmented regions by introducing air gaps between adjacent gate patterns. This segmentation electrically isolates floating gates that are not directly connected, preventing parasitic capacitance and tunnel coupling while maintaining structural organization through defined air gap regions.
Solution Approach 2:
The patent extracts material from the insulating layer to create air gaps between gate patterns. By removing portions of the insulating layer selectively, air gaps are formed that electrically isolate adjacent floating gates, eliminating harmful electrical interactions while preserving the necessary insulating structures.
2Reliability
If air gaps are formed between gate patterns, then parasitic capacitance and tunnel coupling are reduced, but manufacturing process complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming the air gaps between gate patterns before completing subsequent manufacturing steps. The air gaps are created in the insulating layer prior to forming additional structures, allowing the isolation effect to be established early in the process while simplifying later steps that would otherwise require more complex patterning or etching.
3Reliability
If air gaps are formed by removing insulating layer material, then electrical isolation between floating gates is improved, but manufacturing steps increase
Solution Approach 1:
The patent merges multiple functions into the air gap structure itself. The air gaps serve simultaneously as electrical isolation barriers, define active region boundaries, and provide mechanical support for overlying structures. This consolidation reduces the need for separate manufacturing steps that would otherwise be required to achieve these functions independently.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively prevents parasitic capacitance and tunnel coupling by creating a sufficient air gap, enhancing the operational reliability and performance of semiconductor devices by reducing unwanted electrical interactions between adjacent floating gates.
Implementation Method 1
The tunnel insulating layer may be formed by thermally oxidizing the substrate
Implementation Method 2
the capping layer patterns may be formed by thermally oxidizing the gate patterns
Data Source
AI summary
A method of manufacturing a semiconductor device, the method including forming a tunnel insulating layer on an upper surface of a substrate, forming gate patterns on an upper surface of the tunnel insulating layer, forming capping layer patterns on sidewalls of the gate patterns and on the upper surface of the tunnel insulating layer, etching a portion of the tunnel insulating layer that is not covered with the gate patterns or the capping layer patterns to form a tunnel insulating layer pattern, and forming a first insulating layer on the upper surface of the substrate to cover the gate patterns, the capping layer patterns, and the tunnel insulating layer pattern, wherein the first insulating layer has an air gap between the capping layer patterns.