Semiconductor Air Gap Formation for Parasitic Capacitance Reduction
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Solution Overview
Problem
As semiconductor devices become more highly integrated, parasitic capacitance and cell coupling between gate structures or word lines occur due to the high-k characteristics of dielectric layer structures, which are not sufficiently prevented by existing air gaps, affecting the reliability of these devices.
Innovation Solution
A method of manufacturing semiconductor devices with air gaps is developed, involving the sequential formation of a dielectric layer structure and a control gate layer on a substrate, followed by etching to form control gates and spacers, and the use of sacrificial and gate spacers to create air gaps between adjacent structures, which are then covered by an insulating interlayer, effectively reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the distance between gate structures is reduced to increase integration, then device density is improved, but parasitic capacitance and cell coupling increase
Solution Approach 1:
The patent extracts the dielectric material between adjacent gate structures by forming air gaps, removing the harmful dielectric that causes parasitic capacitance and cell coupling. This is achieved through selective etching of the dielectric layer structure between gate electrodes while maintaining the dielectric layer underneath the gate electrodes, thereby eliminating the harmful electromagnetic coupling while preserving device integration density.
Solution Approach 2:
The patent applies different dielectric configurations to different spatial locations: air gaps are formed between adjacent gate structures where parasitic capacitance occurs, while the dielectric layer structure is maintained underneath the gate electrodes where electrical field confinement is needed. This local differentiation allows simultaneous reduction of parasitic effects and maintenance of device performance.
2Object-generated harmful factors
If air gaps are formed between gate electrodes to reduce parasitic capacitance, then cell coupling is reduced, but the dielectric layer structure between gate electrodes must be etched
Solution Approach 1:
The patent segments the dielectric layer structure into two functional regions: the dielectric layer underneath the gate electrodes is maintained to provide electrical field confinement, while the dielectric layer structure between adjacent gate electrodes is removed to form air gaps. This segmentation allows selective etching that reduces cell coupling while maintaining necessary electrical characteristics, simplifying the overall process by avoiding complete removal of dielectric materials.
3Object-generated harmful factors
If the dielectric layer structure is etched to expand air gaps, then parasitic capacitance is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent introduces a sacrificial layer as an intermediary element that facilitates controlled formation of air gaps. The sacrificial layer is deposited between the gate electrodes and the dielectric layer structure, then selectively removed through etching. This intermediary approach provides a buffer that enables precise control of etching depth, ensuring that the dielectric layer underneath the gate electrodes is not damaged while achieving adequate air gap formation to reduce parasitic capacitance.
Data Source
AI summary
In a method of manufacturing a semiconductor device, a dielectric layer structure and a control gate layer can be formed sequentially on a substrate. The control gate layer can be partially etched to form a plurality of control gates. A gate spacer and a sacrificial spacer sequentially can be stacked on a sidewall of the control gate and on a portion of the dielectric layer structure. The dielectric layer structure can be partially etched using the sacrificial spacer and the gate spacer as an etching mask to form a plurality of dielectric layer structure patterns. The sacrificial spacer can be removed. An insulating interlayer can be formed on the substrate to form an air gap. The insulating interlayer can cover the dielectric layer structure pattern, the gate spacer and the control gate. The air gap can extend between the adjacent gate spacers and between the adjacent dielectric layer structure patterns.