Semiconductor Patterning with Air Gaps for Planar Etching Control

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Solution Overview

Problem

The semiconductor industry faces challenges in achieving precise control of lithography across a wafer, particularly in advanced technology process nodes, leading to uneven etching results and reduced device performance.

Innovation Solution

A method is developed that involves forming a first patterned layer over a substrate, followed by a conformal layer and a second layer deposited blanketly. A first etching exposes the first patterned layer, forming a second patterned layer alternately arranged. Vertical portions of the conformal layer are removed, and a sacrificial layer is formed to define air gaps, with a second etching exposing these gaps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional lithography patterning is used in advanced technology nodes, then device density increases, but lithography control precision deteriorates leading to uneven etching

Engineering Contradiction:

Improvelithography control precisionVSAvoiddevice density

Core Design Contradiction:

Manufacturing precisionVSProductivity

Solution Approach 1:

The patterning process is divided into multiple steps: forming a first patterned layer, depositing a conformal layer, performing blanket deposition to form a second layer, and conducting selective etching to create a second patterned layer. This multi-stage segmentation allows each step to be optimized independently, maintaining precision while achieving high device density

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A conformal layer is formed over the first patterned layer before the main patterning step. This preliminary action creates a uniform base that compensates for underlying topography variations, ensuring consistent etching results and maintaining lithography control precision across the entire wafer

Inventive Principle:

Principle #10Preliminary action

2Reliability

If blanket deposition is performed to form the second layer, then material coverage is improved, but process complexity increases

Engineering Contradiction:

Improvematerial coverageVSAvoidprocess complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The conformal layer is deposited beforehand to create a uniform foundation. This preliminary action ensures that subsequent blanket deposition of the second layer achieves consistent material coverage across the wafer, compensating for any underlying surface variations and improving overall process reliability

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The conformal layer acts as an intermediary between the substrate and the second patterned layer. It provides a controlled interface that facilitates uniform material deposition and simplifies the overall process by decoupling the complexity of achieving uniform coverage from the main patterning steps

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method ensures a planar surface of the pattern, avoiding uneven etching and improving device performance and product yield by maintaining precise control over lithography and patterning processes.

Implementation Method 1

forming a conformal layer over the first patterned layer

Methodology Applied

Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

forming a conformal layer over the first patterned layer

Methodology Applied

Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Implementation Method 3

performing a blanket deposition thereby forming a second layer over the conformal layer

Methodology Applied

Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 4

performing a blanket deposition thereby forming a second layer over the conformal layer

Methodology Applied

Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Implementation Method 5

performing a first etching until the first patterned layer is exposed

Methodology Applied

Scientific EffectReactive Ion Etching:

Implementation Method 6

performing a first etching until the first patterned layer is exposed

Methodology Applied

Scientific EffectPlasma Etching:

Data Source

PatentUS20250105016A1Method of manufacturing semiconductor structure

Publication Date: 2025.03.27 NAN YA TECH

AI summary

The present disclosure provides a method of manufacturing a semiconductor structure. A first patterned layer and a second patterned layer are formed over a substrate. The second patterned layer and the first patterned layer are alternately arranged. An etching is performed, thereby forming an arched surface of the first patterned layer and an arched surface of the second patterned layer. A sacrificial layer is formed over the first patterned layer and the second patterned layer, wherein a plurality of air gaps are defined by the substrate, the first patterned layer, the second patterned layer and the sacrificial layer. The sacrificial layer above the plurality of air gaps is removed, and a planar top surface of the first patterned layer and a planar top surface of the second patterned are thereby formed. The substrate is then patterned using the first patterned layer and the second patterned layer as a mask.