Semiconductor Air Gap Spacer for Parasitic Capacitance Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices integrate more densely, parasitic capacitance between conductive structures increases due to their proximity, leading to worsened RC delay and amplified signal sensing issues in DRAMs, necessitating a method to reduce parasitic capacitance.
Innovation Solution
A method is developed to manufacture a semiconductor structure with an air gap by forming a precursor structure with spacer layers and an oxide layer, etching to create an air gap between these layers, and sealing it with a third spacer layer, utilizing nitride and doped oxide materials with selective etching to reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high integration is implemented to increase device density, then productivity is improved, but parasitic capacitance increases due to decreased distance between conductive structures
Solution Approach 1:
The patent introduces an air gap that segments the continuous dielectric medium into separate regions, electrically isolating adjacent conductive structures (bit line and word line) and reducing parasitic capacitance while maintaining high device density
Solution Approach 2:
The air gap acts as an intermediary layer between the bit line and word line, providing electrical insulation and reducing capacitive coupling without requiring additional conductive materials or complex structures
2Productivity
If distance between conductive structures is decreased to increase integration, then productivity is improved, but RC delay worsens due to increased parasitic capacitance
Solution Approach 1:
The air gap segments the electrical field between conductive structures, reducing capacitive coupling and improving RC delay characteristics while maintaining small feature sizes for high integration
3Object-generated harmful factors
If air gap is formed by complete removal of spacer oxide layer, then parasitic capacitance is reduced, but manufacturing complexity increases due to additional sealing requirements
Solution Approach 1:
The third spacer layer is selectively formed only at specific locations where air gap sealing is required, rather than covering the entire structure, thus reducing manufacturing complexity while still achieving the desired parasitic capacitance reduction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces parasitic capacitance by creating an air gap that electrically insulates adjacent conductive structures, improving RC delay and signal sensing in DRAMs by minimizing capacitive coupling.
Implementation Method 1
The spacer oxide layer has an etching selectivity higher than the first spacer layer and the second spacer layer
Implementation Method 2
etching the remaining spacer oxide layer includes using an etchant including hydrofluoric (HF) acid to etch from a bottom of the remaining spacer oxide layer
Implementation Method 3
the semiconductor structure further includes a second conductive structure adjacent to the first conductive structure, wherein the second conductive structure is separated from the first conductive structure by the air gap
Data Source
AI summary
A method of manufacturing a semiconductor structure includes forming a precursor structure on a substrate. The precursor structure includes a first conductive structure, a first spacer layer, and a spacer oxide layer sequentially on the substrate. The spacer oxide layer exposes a top surface of the first spacer layer. The spacer oxide layer is then recessed. A second spacer layer is formed to cover the spacer oxide layer and the first spacer layer. A portion of the second spacer layer and a portion of the spacer oxide layer are then etched to expose the lateral portion of the first spacer layer. The remaining spacer oxide layer is etched to form an air gap between the first spacer layer and the second spacer layer. A third spacer layer is formed on the lateral portion of the first spacer layer to seal the air gap.