Semiconductor Device Air Gap Spacer Parasitic Capacitance
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Solution Overview
Problem
Conventional semiconductor devices face increased parasitic capacitance between the source/drain region and the gate due to the raised source/drain regions covering the sidewall of the spacer, which affects the device's performance.
Innovation Solution
A method is introduced to form a narrow air gap between the spacer and the substrate, allowing the raised portion of the source/drain region to grow away from the spacer, thereby preventing coverage and reducing parasitic capacitance. This is achieved by creating a deep recess and an air gap before forming the source/drain region through epitaxial growth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the raised portion grows along the sidewall of the spacer, then the source/drain region is formed, but parasitic capacitance between source/drain region and gate increases
Solution Approach 1:
Instead of allowing the raised source/drain region to grow directly along the spacer sidewall (conventional approach), the patent inverts the approach by first forming an air gap adjacent to the spacer, then forming the raised source/drain region. This inversion prevents direct contact between the raised region and spacer, reducing parasitic capacitance while maintaining manufacturability.
Solution Approach 2:
The patent introduces a new spatial dimension by creating an air gap between the raised source/drain region and the gate/spacer structure. This dimensional separation in the vertical direction reduces the capacitive coupling area, thereby reducing parasitic capacitance while preserving the source/drain region formation process.
2Ease of manufacture
If the raised portion directly covers the lower sidewall of the spacer, then source/drain region is formed, but parasitic capacitance between source/drain region and gate increases
Solution Approach 1:
The patent extracts the harmful interaction between the raised source/drain region and the spacer by removing the direct contact between them. An air gap is introduced to separate these two structures, taking out the parasitic capacitance component while preserving the source/drain region formation process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach effectively reduces parasitic capacitance by directing the epitaxial growth away from the spacer, enhancing the semiconductor device's performance by minimizing unwanted capacitance.
Implementation Method 1
One method for forming a strained silicon channel is forming the source/drain regions as the stressors at two sides of the channel by selective epitaxial growth (SEG).
Implementation Method 2
The epitaxial layers of the source/drain regions may have a lattice arrangement different from the lattice constant of the substrate (the channel) by comprising dopants. The mismatch of the lattice constants between the source/drain regions and the substrate may induce a desired type and magnitude of stress to the channel region
Data Source
AI summary
A semiconductor device is disclosed. The semiconductor device comprises a substrate, a gate structure disposed on the substrate, a spacer disposed on the substrate and covering a sidewall of the gate structure, an air gap sandwiched between the spacer and the substrate, and a source/drain region disposed in the substrate and having a faceted surface exposed from the substrate, wherein the faceted surface borders the substrate on a boundary between the air gap and the substrate.