Backside Semiconductor Air Gaps for Low-Capacitance Power Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor fabrication methods fail to effectively reduce resistance and coupling capacitance in power rails and vias on the backside of integrated circuits, leading to increased voltage drop and power consumption as circuits scale down.
Innovation Solution
The introduction of backside metal wiring layers and air gaps interposed between gate stacks and power rails, utilizing a bottom self-aligned capping layer with a high dielectric constant to reduce coupling capacitance and prevent leakage paths, while allowing for wider power rails to decrease resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power rails are made wider to reduce resistance, then voltage drop is reduced, but coupling capacitance between power rails and gate stacks increases
Solution Approach 1:
A low-k dielectric layer is introduced as an intermediary material between the power rail and the gate stack. This intermediate layer reduces the coupling capacitance while allowing the power rail to maintain its wider configuration for lower resistance, thus resolving the contradiction between reducing voltage drop and minimizing coupling capacitance.
Solution Approach 2:
The dielectric layer is applied selectively in the region where the power rail intersects with or approaches the gate stack. This localized application reduces coupling capacitance only where it is harmful, while allowing the power rail to maintain its overall wider structure for reduced resistance elsewhere.
2Productivity
If power rails are scaled down to maintain circuit scaling, then circuit density increases, but resistance and voltage drop increase
Solution Approach 1:
The power rail structure is extended into the vertical dimension by adding multiple stacked metal layers. This allows the power distribution network to maintain adequate cross-sectional area for low resistance while occupying less lateral space, thus supporting higher circuit density without increasing voltage drop.
Solution Approach 2:
The power rail structure utilizes composite construction with multiple metal layers stacked vertically, each layer contributing to the overall conductive cross-section. This composite approach enables the power delivery system to achieve low resistance equivalent to wider single-layer rails while maintaining a smaller lateral footprint for higher device density.
3Device complexity
If conventional fabrication processes are used, then manufacturing complexity is low, but coupling capacitance and resistance cannot be effectively reduced
Solution Approach 1:
The low-k dielectric layer is deposited and patterned in advance, before the power rail metal layers are formed. This preliminary preparation of the dielectric structure enables subsequent power rail fabrication to proceed with standard processes, while the pre-positioned dielectric already provides the capacitance reduction function.
Solution Approach 2:
The low-k dielectric layer serves multiple functions: it acts as an insulating barrier, reduces coupling capacitance, and provides a planarization surface for subsequent metal deposition. This multi-functionality allows the structure to achieve performance improvements without requiring separate dedicated process steps for each function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces coupling capacitance, enhances IC performance by allowing faster operation, and increases gate density for greater device integration without increasing power rail resistance, thereby addressing the limitations of existing methods.
Implementation Method 1
utilizing a bottom self-aligned capping layer with a high dielectric constant to reduce coupling capacitance
Implementation Method 2
The air gaps may extend from a bottom self-aligned capping (B-SAC) layer to a seal layer
Data Source
AI summary
A semiconductor structure includes first and second source/drain (S/D) features, one or more semiconductor channel layers connecting the first and second S/D features, a gate structure engaging the one or more semiconductor channel layers, a metal wiring layer at a backside of the semiconductor structure, an S/D contact electrically connecting the first S/D feature to the metal wiring layer, and a seal layer between the metal wiring layer and the gate structure. The seal layer is spaced away from the gate structure by an air gap therebetween.