Semiconductor Air Gaps Reduce Parasitic Capacitance
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Solution Overview
Problem
As semiconductor devices become more integrated, parasitic capacitance increases due to the proximity of conductive structures, degrading performance and limiting the effectiveness of existing methods to reduce capacitance by lowering the permittivity of dielectric materials.
Innovation Solution
The semiconductor device incorporates air gaps of varying widths between conductive structures, including line-shaped and plug-shaped air gaps, formed by removing sacrificial layers, to reduce parasitic capacitance, with silicon nitride spacers and capping layers enhancing the structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the distance between conductive structures is reduced to achieve high integration, then device integration density is improved, but parasitic capacitance increases
Solution Approach 1:
The patent extracts the harmful dielectric material between adjacent conductive structures and replaces it with air gaps. Specifically, sacrificial liner layers are removed to create air gaps between the bit line and storage node contact plug, eliminating the source of parasitic capacitance while maintaining the high integration layout
Solution Approach 2:
The patent applies different gap configurations at different locations to optimize capacitance reduction. Line-shaped air gaps are formed between the bit line and storage node contact plug, while plug-shaped air gaps are formed between adjacent storage node contact plugs. This localized quality approach allows targeted capacitance reduction where most needed
2Object-generated harmful factors
If the permittivity of dielectric material is lowered to reduce parasitic capacitance, then capacitance is reduced, but the effect is limited due to material constraints
Solution Approach 1:
The patent introduces air gaps (gas phase) between conductive structures to replace solid dielectric materials. By using air as the insulating medium with permittivity close to 1, the patent achieves maximum capacitance reduction without being constrained by dielectric material selection, effectively applying the pneumatic principle to electrical insulation
3Object-generated harmful factors
If air gaps are formed between conductive structures to reduce parasitic capacitance, then parasitic capacitance is reduced, but device complexity increases
Solution Approach 1:
The patent forms sacrificial liner layers (silicon oxide) during the standard contact plug fabrication process before finalizing the conductive structures. These preliminary sacrificial layers are then selectively removed to create air gaps, allowing the complex gap formation to be integrated into the existing fabrication flow without requiring entirely new process steps
Data Source
AI summary
A semiconductor device may include: a substrate having first and second surfaces; an interlayer dielectric layer having a first opening to expose the first surface; a first plug positioned in the first opening and isolated from a sidewall of the first opening by a pair of gaps; a bit line extended in any one direction while covering the first plug; a second plug including a lower part adjacent to the first plug and an upper part adjacent to the bit line, and connected to the second surface; a first air gap positioned between the first plug and the lower part of the second plug; and a second air gap positioned between the bit line and the upper part of the second plug, and having a larger width than the first air gap.