Semiconductor Air Space Support for Capacitance Reduction
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Solution Overview
Problem
The increasing integration density of semiconductor devices leads to shorter distances between interconnection lines and contact plugs, resulting in higher load capacitances that can negatively impact operating speed and refresh characteristics.
Innovation Solution
A semiconductor device design featuring a substrate with conductive lines, insulating capping lines, and contact plugs, where supports are interposed between the insulating capping lines and contact plugs to create air spaces, with the support's width varying or being discontinuous, reducing capacitance by limiting the height of these spaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If integration density is increased to reduce device size, then device miniaturization is achieved, but load capacitance between adjacent conductive patterns increases
Solution Approach 1:
Air spaces are introduced as intermediary regions between adjacent conductive patterns (bit lines and contact plugs). These air spaces act as mediators that reduce the dielectric constant in the region between conductive elements, thereby reducing parasitic capacitance while maintaining the miniaturized device structure
Solution Approach 2:
The dielectric parameter (dielectric constant) is changed by replacing traditional dielectric materials with air spaces in critical regions between conductive patterns. This parameter change reduces the capacitance value without requiring larger spacing between elements, thus resolving the contradiction between miniaturization and capacitance reduction
2Productivity
If distance between interconnection lines and contact plugs is reduced to increase integration density, then device integration is improved, but operating speed deteriorates due to higher capacitance
Solution Approach 1:
Air spaces serve as intermediary regions that allow closer spacing between bit lines and contact plugs while maintaining low capacitance. This enables high integration density without the penalty of increased capacitance that would normally slow down signal transitions and refresh operations
3Object-affected harmful factors
If support width is reduced to minimize capacitance, then load capacitance is reduced, but structural support may be compromised
Solution Approach 1:
The support structure is designed with spatially varying width - wider regions where mechanical support is needed and narrower regions where capacitance reduction is prioritized. This local differentiation of support quality allows the structure to maintain sufficient strength while minimizing capacitance in critical areas
Solution Approach 2:
The support is divided into multiple segments with different widths along its length. This segmentation allows optimization of each segment's width based on local requirements - providing structural support where needed and reducing capacitance where adjacent conductive elements are positioned
Data Source
AI summary
A semiconductor device includes a stack structure of a conductive line and an insulating capping line extending in a first direction on a substrate, a plurality of contact plugs arranged in a row along the first direction and having sidewall surfaces facing the conductive line with air spaces between the sidewall surfaces and the conductive line, and a support interposed between the insulating capping line and the contact plugs to limit the height of the air spaces. The width of the support varies or the support is present only intermittently in the first direction. In a method of manufacturing the semiconductor devices, a sacrificial spacer is formed on the side of the stack structure, the spacer is recessed, a support layer is formed in the recess, the support layer is etched to form the support, and then the remainder of the spacer is removed to provide the air spaces.